| 2009 |
|---|
| 69 | EE | Hiroki Sunagawa,
Haruhiko Terada,
Akira Tsuchiya,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Erect of regularity-enhanced layout on printability and circuit performance of standard cells.
ISQED 2009: 195-200 |
| 2008 |
|---|
| 68 | EE | Takayuki Fukuoka,
Akira Tsuchiya,
Hidetoshi Onodera:
Statistical gate delay model for Multiple Input Switching.
ASP-DAC 2008: 286-291 |
| 67 | EE | Kazutoshi Kobayashi,
Hidetoshi Onodera:
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs.
ASP-DAC 2008: 811-812 |
| 66 | EE | Yuuri Sugihara,
Yohei Kume,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.
FPGA 2008: 257 |
| 65 | EE | Kazutoshi Kobayashi,
Yohei Kume,
Cam Lai Ngo,
Yuuri Sugihara,
Hidetoshi Onodera:
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.
FPL 2008: 107-112 |
| 64 | EE | Yuuri Sugihara,
Yohei Kume,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.
FPL 2008: 503-506 |
| 63 | EE | Masanori Hashimoto,
Junji Yamaguchi,
Takashi Sato,
Hidetoshi Onodera:
Timing Analysis Considering Temporal Supply Voltage Fluctuation.
IEICE Transactions 91-D(3): 655-660 (2008) |
| 2007 |
|---|
| 62 | EE | Takeshi Kuboki,
Akira Tsuchiya,
Hidetoshi Onodera:
A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.
ASP-DAC 2007: 120-121 |
| 61 | EE | Yuuri Sugihara,
Manabu Kotani,
Kazuya Katsuki,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.
ASP-DAC 2007: 122-123 |
| 60 | EE | Takayuki Fukuoka,
Akira Tsuchiya,
Hidetoshi Onodera:
Worst-case delay analysis considering the variability of transistors and interconnects.
ISPD 2007: 35-42 |
| 59 | EE | Masanori Hashimoto,
Junji Yamaguchi,
Hidetoshi Onodera:
Timing Analysis Considering Spatial Power/Ground Level Variation.
IEICE Transactions 90-A(12): 2661-2668 (2007) |
| 58 | EE | Hirokazu Muta,
Hidetoshi Onodera:
Manufacturability-Aware Design of Standard Cells.
IEICE Transactions 90-A(12): 2682-2690 (2007) |
| 57 | EE | Kazutoshi Kobayashi,
Kazuya Katsuki,
Manabu Kotani,
Yuuri Sugihara,
Yohei Kume,
Hidetoshi Onodera:
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.
IEICE Transactions 90-C(10): 1919-1926 (2007) |
| 56 | EE | Kazuya Katsuki,
Manabu Kotani,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.
IEICE Transactions 90-C(4): 699-707 (2007) |
| 55 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling.
IEICE Transactions 90-C(6): 1267-1273 (2007) |
| 54 | EE | Takeshi Kuboki,
Akira Tsuchiya,
Hidetoshi Onodera:
Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver.
IEICE Transactions 90-C(6): 1274-1281 (2007) |
| 2006 |
|---|
| 53 | EE | Kazuya Katsuki,
Manabu Kotani,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.
ASP-DAC 2006: 110-111 |
| 52 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Interconnect RL extraction at a single representative frequency.
ASP-DAC 2006: 515-520 |
| 51 | EE | Kazutoshi Kobayashi,
Manabu Kotani,
Kazuya Katsuki,
Y. Takatsukasa,
K. Ogata,
Yuuri Sugihara,
Hidetoshi Onodera:
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.
FPL 2006: 1-4 |
| 50 | EE | Hidetoshi Onodera:
Special Section on VLSI Design and CAD Algorithms.
IEICE Transactions 89-A(12): 3377 (2006) |
| 49 | EE | Toshiki Kanamoto,
Tatsuhiko Ikeda,
Akira Tsuchiya,
Hidetoshi Onodera,
Masanori Hashimoto:
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.
IEICE Transactions 89-A(12): 3560-3568 (2006) |
| 48 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line.
IEICE Transactions 89-A(12): 3585-3593 (2006) |
| 47 | EE | Yoichi Yuyama,
Akira Tsuchiya,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect.
IEICE Transactions 89-C(3): 327-333 (2006) |
| 46 | EE | Hidetoshi Onodera:
Variability: Modeling and Its Impact on Design.
IEICE Transactions 89-C(3): 342-348 (2006) |
| 45 | EE | Kazutoshi Kobayashi,
Akihiko Higuchi,
Hidetoshi Onodera:
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era.
IEICE Transactions 89-C(6): 838-843 (2006) |
| 2005 |
|---|
| 44 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Return path selection for loop RL extraction.
ASP-DAC 2005: 1078-1081 |
| 43 | EE | Masanori Hashimoto,
Junji Yamaguchi,
Takashi Sato,
Hidetoshi Onodera:
Timing analysis considering temporal supply voltage fluctuation.
ASP-DAC 2005: 1098-1101 |
| 42 | EE | Kazutoshi Kobayashi,
Masao Aramoto,
Yoichi Yuyama,
Akihiko Higuchi,
Hidetoshi Onodera:
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.
ASP-DAC 2005: 619-622 |
| 41 | EE | Takashi Sato,
Masanori Hashimoto,
Hidetoshi Onodera:
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion.
ASP-DAC 2005: 723-728 |
| 40 | EE | Akinori Shinmyo,
Masanori Hashimoto,
Hidetoshi Onodera:
Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process.
ASP-DAC 2005: 9-10 |
| 39 | EE | Atsushi Muramatsu,
Masanori Hashimoto,
Hidetoshi Onodera:
Effects of on-chip inductance on power distribution grid.
ISPD 2005: 63-69 |
| 38 | EE | Masanori Hashimoto,
Tomonori Yamamoto,
Hidetoshi Onodera:
Statistical Analysis of Clock Skew Variation in H-Tree Structure.
ISQED 2005: 402-407 |
| 37 | EE | Masanori Hashimoto,
Tomonori Yamamoto,
Hidetoshi Onodera:
Statistical Analysis of Clock Skew Variation in H-Tree Structure.
IEICE Transactions 88-A(12): 3375-3381 (2005) |
| 36 | EE | Takashi Sato,
Masanori Hashimoto,
Hidetoshi Onodera:
Successive Pad Assignment for Minimizing Supply Voltage Drop.
IEICE Transactions 88-A(12): 3429-3436 (2005) |
| 35 | EE | Atsushi Muramatsu,
Masanori Hashimoto,
Hidetoshi Onodera:
Effects of On-Chip Inductance on Power Distribution Grid.
IEICE Transactions 88-A(12): 3564-3572 (2005) |
| 34 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling.
IEICE Transactions 88-A(4): 885-891 (2005) |
| 33 | EE | Takahito Miyazaki,
Masanori Hashimoto,
Hidetoshi Onodera:
A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL.
IEICE Transactions 88-C(3): 437-444 (2005) |
| 32 | EE | Kazutoshi Kobayashi,
Masao Aramoto,
Hidetoshi Onodera:
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era.
IEICE Transactions 88-C(4): 552-558 (2005) |
| 2004 |
|---|
| 31 | EE | Takahito Miyazaki,
Masanori Hashimoto,
Hidetoshi Onodera:
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process.
ASP-DAC 2004: 545-546 |
| 30 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Representative frequency for interconnect R(f)L(f)C extraction.
ASP-DAC 2004: 691-696 |
| 29 | EE | Yoichi Yuyama,
Masao Aramoto,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
An SoC architecture and its design methodology using unifunctional heterogeneous processor array.
ASP-DAC 2004: 737-742 |
| 28 | EE | Masanori Hashimoto,
Junji Yamaguchi,
Hidetoshi Onodera:
Timing analysis considering spatial power/ground level variation.
ICCAD 2004: 814-820 |
| 27 | | Ken-ichi Okada,
Hiroaki Hoshino,
Hidetoshi Onodera:
Modelling and optimization of on-chip spiral inductor in S-parameter domain.
ISCAS (5) 2004: 153-156 |
| 26 | | Yoichi Yuyama,
Masao Aramoto,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
RTL/ISS co-modeling methodology for embedded processor using SystemC.
ISCAS (5) 2004: 305-308 |
| 25 | EE | Masanori Hashimoto,
Kazunori Fujimori,
Hidetoshi Onodera:
Automatic Generation of Standard Cell Library in VDSM Technologies.
ISQED 2004: 36-41 |
| 24 | EE | Masanori Hashimoto,
Yuji Yamada,
Hidetoshi Onodera:
Equivalent waveform propagation for static timing analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 498-508 (2004) |
| 2003 |
|---|
| 23 | EE | Masanori Hashimoto,
Yuji Yamada,
Hidetoshi Onodera:
Equivalent Waveform Propagation for Static Timing Analysis.
ICCAD 2003: 169-175 |
| 22 | EE | Ken-ichi Okada,
Kento Yamaoka,
Hidetoshi Onodera:
A Statistical Gate-Delay Model Considering Intra-Gate Variability.
ICCAD 2003: 908-913 |
| 21 | EE | Ken-ichi Okada,
Kento Yamaoka,
Hidetoshi Onodera:
Statistical modeling of gate-delay variation with consideration of intra-gate variability.
ISCAS (5) 2003: 513-516 |
| 20 | EE | Masanori Hashimoto,
Yuji Yamada,
Hidetoshi Onodera:
Capturing crosstalk-induced waveform for accurate static timing analysis.
ISPD 2003: 18-23 |
| 2002 |
|---|
| 19 | EE | Masanori Hashimoto,
Masao Takahashi,
Hidetoshi Onodera:
Crosstalk noise optimization by post-layout transistor sizing.
ISPD 2002: 126-130 |
| 18 | | Masanori Hashimoto,
Yashiteru Hayashi,
Hidetoshi Onodera:
Experimental Study on Cell-Base High-Performance Datapath Design.
IWLS 2002: 283-287 |
| 2001 |
|---|
| 17 | EE | Kazutoshi Kobayashi,
Makoto Eguchi,
Takuya Iwahashi,
Takehide Shibayama,
Xiang Li,
Kousuke Takai,
Hidetoshi Onodera:
A vector-pipeline DSP for low-rate videophones.
ASP-DAC 2001: 1-2 |
| 16 | EE | Hidetoshi Onodera,
Andrew B. Kahng,
Wayne Wei-Ming Dai,
Sani R. Nassif,
Juho Kim,
Akira Tanabe,
Toshihiro Hattori:
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.
ASP-DAC 2001: 267-268 |
| 15 | EE | Takeo Yasuda,
Hiroaki Fujita,
Hidetoshi Onodera:
A dynamically phase adjusting PLL with a variable delay.
ASP-DAC 2001: 275-280 |
| 14 | EE | Masanori Hashimoto,
Hidetoshi Onodera:
Post-layout transistor sizing for power reduction in cell-based design.
ASP-DAC 2001: 359-365 |
| 13 | | Masao Takahashi,
Masanori Hashimoto,
Hidetoshi Onodera:
Crosstalk Noise Estimation for Generic RC Trees.
ICCD 2001: 110-117 |
| 12 | EE | Kazutoshi Kobayashi,
Hidetoshi Onodera:
ST: PERL package for simulation and test environment.
ISCAS (5) 2001: 89-92 |
| 2000 |
|---|
| 11 | EE | Tomohiro Fujita,
Ken-ichi Okada,
Hiroaki Fujita,
Hidetoshi Onodera,
Keikichi Tamaru:
A method for linking process-level variability to system performances.
ASP-DAC 2000: 547-552 |
| 10 | EE | Masanori Hashimoto,
Hidetoshi Onodera:
A performance optimization method by gate sizing using statistical static timing analysis.
ISPD 2000: 111-116 |
| 1999 |
|---|
| 9 | EE | Masanori Hashimoto,
Hidetoshi Onodera,
Keikichi Tamaru:
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.
DAC 1999: 446-451 |
| 1998 |
|---|
| 8 | EE | Akio Hirata,
Hidetoshi Onodera,
Keikichi Tamaru:
Proposal of a timing model for CMOS logic gates driving a CRC load.
ICCAD 1998: 537-544 |
| 7 | EE | Masanori Hashimoto,
Hidetoshi Onodera,
Keikichi Tamaru:
A power optimization method considering glitch reduction by gate sizing.
ISLPED 1998: 221-226 |
| 6 | EE | Masaki Kondo,
Hidetoshi Onodera,
Keikichi Tamaru:
Model-adaptable MOSFET parameter-extraction method using an intermediate model.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 400-405 (1998) |
| 1996 |
|---|
| 5 | EE | Guangqiu Chen,
Hidetoshi Onodera,
Keikichi Tamaru:
Timing and Power Optimization by Gate Sizing Considering False Paths.
Great Lakes Symposium on VLSI 1996: 154- |
| 1995 |
|---|
| 4 | EE | Masaki Kondo,
Hidetoshi Onodera,
Keikichi Tamaru:
A model-adaptable MOSFET parameter extraction system.
ASP-DAC 1995 |
| 3 | EE | Guangqiu Chen,
Hidetoshi Onodera,
Keikichi Tamaru:
An iterative gate sizing approach with accurate delay evaluation.
ICCAD 1995: 422-427 |
| 1993 |
|---|
| 2 | EE | Vasily G. Moshnyaga,
Hiroshi Mori,
Hidetoshi Onodera,
Keikichi Tamaru:
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's.
ICCAD 1993: 100-103 |
| 1991 |
|---|
| 1 | EE | Hidetoshi Onodera,
Yo Taniguchi,
Keikichi Tamaru:
Branch-and-Bound Placement for Building Block Layout.
DAC 1991: 433-439 |
