2007 |
7 | EE | Tetsuya Yamada,
Naohiko Irie,
Takanobu Tsunoda,
Takahiro Irita,
Kenji Kitagawa,
Ryohei Yoshida,
Keisuke Toyama,
Motoaki Satoyama:
A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core.
IEICE Transactions 90-C(2): 523-530 (2007) |
2006 |
6 | EE | Masafumi Onouchi,
Tetsuya Yamada,
Kimihiro Morikawa,
Isamu Mochizuki,
Hidetoshi Sekine:
A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation.
ASP-DAC 2006: 547-550 |
5 | EE | Toshihiro Hattori,
Takahiro Irita,
Masayuki Ito,
Eiji Yamamoto,
Hisashi Kato,
Go Sado,
Tetsuhiro Yamada,
Kunihiko Nishiyama,
Hiroshi Yagi,
Takao Koike,
Yoshihiko Tsuchihashi,
Motoki Higashida,
Hiroyuki Asano,
Izumi Hayashibara,
Ken Tatezawa,
Yasuhisa Shimazaki,
Naozumi Morino,
Yoshihiko Yasu,
Tadashi Hoshi,
Yujiro Miyairi,
Kazumasa Yanagisawa,
Kenji Hirose,
Saneaki Tamaki,
Shinichi Yoshioka,
Toshifumi Ishii,
Yusuke Kanno,
Hiroyuki Mizuno,
Tetsuya Yamada,
Naohiko Irie,
Reiko Tsuchihashi,
Nobuto Arai,
Tomohiro Akiyama,
Koji Ohno:
Hierarchical power distribution and power management scheme for a single chip mobile processor.
DAC 2006: 292-295 |
4 | EE | Tetsuya Yamada,
Masahide Abe,
Yusuke Nitta,
Kenji Ogura,
Manabu Kusaoke,
Makoto Ishikawa,
Motokazu Ozawa,
Kiwamu Takada,
Fumio Arakawa,
Osamu Nishii,
Toshihiro Hattori:
Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.
IEICE Transactions 89-C(3): 287-294 (2006) |
3 | EE | Fumio Arakawa,
Tetsuya Yamada,
Takashi Okada,
Makoto Ishikawa,
Yuki Kondo,
Motokazu Ozawa,
Tomoyuki Kodama,
Osamu Nishii,
Toshihiro Hattori,
Tatsuya Kamei,
Junichi Nishimoto,
Shinichi Yoshioka:
Development of processor cores for digital consumer appliances.
Systems and Computers in Japan 37(3): 10-19 (2006) |
2005 |
2 | EE | Tetsuya Yamada,
Masahide Abe,
Yusuke Nitta,
Kenji Ogura,
Manabu Kusaoke,
Makoto Ishikawa,
Motokazu Ozawa,
Kiwamu Takada,
Fumio Arakawa,
Osamu Nishii,
Toshihiro Hattori:
Low-Power Design of 90-nm SuperH Processor Core.
ICCD 2005: 258-266 |
1996 |
1 | | Tetsuya Yamada,
Hiroto Yasuura:
On the Computational Power of Binary Decision Diagram with Redundant Variables.
Formal Methods in System Design 8(1): 65-89 (1996) |