| 2008 |
|---|
| 5 | EE | Cheng-Tao Hsieh,
Jason Cong,
Zhiru Zhang,
Shih-Chieh Chang:
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.
ASP-DAC 2008: 10-15 |
| 2007 |
|---|
| 4 | EE | Cheng-Tao Hsieh,
Jian-Cheng Lin,
Shih-Chieh Chang:
Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis.
ISQED 2007: 602-606 |
| 2006 |
|---|
| 3 | EE | Kai-Chiang Wu,
Cheng-Tao Hsieh,
Shih-Chieh Chang:
Delay variation tolerance for domino circuits.
ASP-DAC 2006: 354-359 |
| 2004 |
|---|
| 2 | EE | Shih-Chieh Chang,
Cheng-Tao Hsieh,
Kai-Chiang Wu:
Re-synthesis for delay variation tolerance.
DAC 2004: 814-819 |
| 1 | EE | Cheng-Tao Hsieh,
Jian-Cheng Lin,
Shih-Chieh Chang:
A vectorless estimation of maximum instantaneous current for sequential circuits.
ICCAD 2004: 537-540 |
