| 2007 |
|---|
| 8 | EE | Takeshi Kitahara,
Naoyuki Kawabe,
Fumihiro Minami,
Katsuhiro Seta,
Toshiyuki Furusawa:
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
CoRR abs/0710.4762: (2007) |
| 2006 |
|---|
| 7 | EE | Takeshi Kitahara,
Hiroyuki Hara,
Shinichiro Shiratake,
Yoshiki Tsukiboshi,
Tomoyuki Yoda,
Tetsuaki Utsumi,
Fumihiro Minami:
Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems.
ASP-DAC 2006: 533-540 |
| 2005 |
|---|
| 6 | EE | Takeshi Kitahara,
Naoyuki Kawabe,
Fumihiro Minami,
Katsuhiro Seta,
Toshiyuki Furusawa:
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction.
DATE 2005: 646-647 |
| 2004 |
|---|
| 5 | EE | Sachio Hayashi,
Fumihiro Minami,
Masaaki Yamada:
Full-Chip Analysis Method of ESD Protection Network.
ISQED 2004: 439-444 |
| 1998 |
|---|
| 4 | | Takeshi Kitahara,
Fumihiro Minami,
Toshiaki Ueda,
Kimiyoshi Usami,
Seiichi Nishio,
Masami Murakata,
Takashi Mitsuhashi:
A Clock-Gating Method for Low-Power LSI Design.
ASP-DAC 1998: 307-312 |
| 1997 |
|---|
| 3 | EE | Mutsunori Igarashi,
Kimiyoshi Usami,
Kazutaka Nogami,
Fumihiro Minami,
Yukio Kawasaki,
Takahiro Aoki,
Midori Takano,
Chiharo Mizuno,
Takashi Ishikawa,
Masahiro Kanazawa,
Shinji Sonoda,
Makoto Ichida,
Naoyuki Hatanaka:
A low-power design method using multiple supply voltages.
ISLPED 1997: 36-41 |
| 1996 |
|---|
| 2 | EE | Taku Uchino,
Fumihiro Minami,
Masami Murakata,
Takashi Mitsuhashi:
Switching activity analysis for sequential circuits using Boolean approximation method.
ISLPED 1996: 79-84 |
| 1995 |
|---|
| 1 | EE | Taku Uchino,
Fumihiro Minami,
Takashi Mitsuhashi,
Nobuyuki Goto:
Switching activity analysis using Boolean approximation method.
ICCAD 1995: 20-25 |
