Munehiro Matsuura

2009
21	EE	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura: A Parallel Branching Program Machine for Emulation of Sequential Circuits. ARC 2009: 261-267
2007
20	EE	Tsutomu Sasao, Munehiro Matsuura: An Implementation of an Address Generator Using Hash Memories. DSD 2007: 69-76
19	EE	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A CAM Emulator Using Look-Up Table Cascades. IPDPS 2007: 1-8
18	EE	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. ISMVL 2007: 32
17	EE	Munehiro Matsuura, Tsutomu Sasao: BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades. IEICE Transactions 90-A(12): 2762-2769 (2007)
16	EE	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Design Methods of Radix Converters Using Arithmetic Decompositions. IEICE Transactions 90-D(6): 905-914 (2007)
2006
15	EE	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A fast logic simulator using a look up table cascade emulator. ASP-DAC 2006: 466-472
14	EE	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: On Designs of Radix Converters Using Arithmetic Decompositions. ISMVL 2006: 3
13	EE	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator. IEICE Transactions 89-A(12): 3471-3481 (2006)
2005
12	EE	Tsutomu Sasao, Munehiro Matsuura: BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. DAC 2005: 373-378
11	EE	Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura: Average Path Length of Binary Decision Diagrams. IEEE Trans. Computers 54(9): 1041-1053 (2005)
10	EE	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura: A Design Algorithm for Sequential Circuits Using LUT Rings. IEICE Transactions 88-A(12): 3342-3350 (2005)
2004
9	EE	Tsutomu Sasao, Munehiro Matsuura: A method to decompose multiple-output logic functions. DAC 2004: 428-433
8	EE	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. ISMVL 2004: 302-308
2002
7	EE	Shinobu Nagayama, Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura: Representations of Logic Functions Using QRMDDs. ISMVL 2002: 261-
6		Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura: Comparison of Decision Diagrams for Multiple-Output Logic Functions. IWLS 2002: 379-384
2001
5		Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Realization of Multiple-Output Functions by Reconfigurable Cascades. ICCD 2001: 388-393
2000
4	EE	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno: A hardware simulation engine based on decision diagrams (short paper). ASP-DAC 2000: 73-76
3	EE	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: Implementation of Multiple-Output Functions Using PQMDDs. ISMVL 2000: 199-205
1999
2	EE	Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno: Realization of Regular Ternary Logic Functions. ASP-DAC 1999: 331-
1997
1	EE	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura: On Decomposition of Kleene TDDs. Asian Test Symposium 1997: 234-

Coauthor Index

1	Jon T. Butler	[11]
2	Yukihiro Iguchi	[1] [2] [3] [4] [5] [6] [7] [8] [14] [16] [18]
3	Atsumu Iseno	[2] [4]
4	Yoshifumi Kawamura	[21]
5	Shinobu Nagayama	[7]
6	Hiroki Nakahara	[10] [13] [15] [19] [21]
7	Tsutomu Sasao	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]