Bakhtiar Affendi Rosdi

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2007

4 EE Bakhtiar Affendi Rosdi, Atsushi Takahashi: Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements. IEICE Transactions 90-A(12): 2736-2742 (2007)

2006

3 EE Bakhtiar Affendi Rosdi, Atsushi Takahashi: Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits. APCCAS 2006: 801-804

2 EE Bakhtiar Affendi Rosdi, Atsushi Takahashi: Low area pipelined circuits by multi-clock cycle paths and clock scheduling. ASP-DAC 2006: 260-265

1 EE Bakhtiar Affendi Rosdi, Atsushi Takahashi: Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits. IEICE Transactions 89-A(12): 3435-3442 (2006)

2007
4	EE	Bakhtiar Affendi Rosdi, Atsushi Takahashi: Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements. IEICE Transactions 90-A(12): 2736-2742 (2007)
2006
3	EE	Bakhtiar Affendi Rosdi, Atsushi Takahashi: Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits. APCCAS 2006: 801-804
2	EE	Bakhtiar Affendi Rosdi, Atsushi Takahashi: Low area pipelined circuits by multi-clock cycle paths and clock scheduling. ASP-DAC 2006: 260-265
1	EE	Bakhtiar Affendi Rosdi, Atsushi Takahashi: Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits. IEICE Transactions 89-A(12): 3435-3442 (2006)

Coauthor Index

1 Atsushi Takahashi [1] [2] [3] [4]