2008 | ||
---|---|---|
3 | EE | Kenta Yamada, Noriaki Oda: Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications). IEICE Transactions 91-C(4): 562-570 (2008) |
2007 | ||
2 | EE | Noriaki Oda, Hironori Imura, Naoyoshi Kawahara, Masayoshi Tagami, Hiroyuki Kunishima, Shuji Sone, Sadayuki Ohnishi, Kenta Yamada, Yumi Kakuhara, Makoto Sekine, Yoshihiro Hayashi, Kazuyoshi Ueno: Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation. IEICE Transactions 90-C(4): 848-855 (2007) |
2006 | ||
1 | EE | Kenta Yamada, Noriaki Oda: Statistical corner conditions of interconnect delay (corner LPE specifications). ASP-DAC 2006: 706-711 |
1 | Yoshihiro Hayashi | [2] |
2 | Hironori Imura | [2] |
3 | Yumi Kakuhara | [2] |
4 | Naoyoshi Kawahara | [2] |
5 | Hiroyuki Kunishima | [2] |
6 | Noriaki Oda | [1] [2] [3] |
7 | Sadayuki Ohnishi | [2] |
8 | Makoto Sekine | [2] |
9 | Shuji Sone | [2] |
10 | Masayoshi Tagami | [2] |
11 | Kazuyoshi Ueno | [2] |