2009 |
18 | EE | Hiroki Sunagawa,
Haruhiko Terada,
Akira Tsuchiya,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Erect of regularity-enhanced layout on printability and circuit performance of standard cells.
ISQED 2009: 195-200 |
2008 |
17 | EE | Kazutoshi Kobayashi,
Hidetoshi Onodera:
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs.
ASP-DAC 2008: 811-812 |
16 | EE | Yuuri Sugihara,
Yohei Kume,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.
FPGA 2008: 257 |
15 | EE | Kazutoshi Kobayashi,
Yohei Kume,
Cam Lai Ngo,
Yuuri Sugihara,
Hidetoshi Onodera:
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.
FPL 2008: 107-112 |
14 | EE | Yuuri Sugihara,
Yohei Kume,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.
FPL 2008: 503-506 |
2007 |
13 | EE | Yuuri Sugihara,
Manabu Kotani,
Kazuya Katsuki,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.
ASP-DAC 2007: 122-123 |
12 | EE | Kazutoshi Kobayashi,
Kazuya Katsuki,
Manabu Kotani,
Yuuri Sugihara,
Yohei Kume,
Hidetoshi Onodera:
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.
IEICE Transactions 90-C(10): 1919-1926 (2007) |
11 | EE | Kazuya Katsuki,
Manabu Kotani,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations.
IEICE Transactions 90-C(4): 699-707 (2007) |
2006 |
10 | EE | Kazuya Katsuki,
Manabu Kotani,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices.
ASP-DAC 2006: 110-111 |
9 | EE | Kazutoshi Kobayashi,
Manabu Kotani,
Kazuya Katsuki,
Y. Takatsukasa,
K. Ogata,
Yuuri Sugihara,
Hidetoshi Onodera:
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.
FPL 2006: 1-4 |
8 | EE | Yoichi Yuyama,
Akira Tsuchiya,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect.
IEICE Transactions 89-C(3): 327-333 (2006) |
7 | EE | Kazutoshi Kobayashi,
Akihiko Higuchi,
Hidetoshi Onodera:
A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era.
IEICE Transactions 89-C(6): 838-843 (2006) |
2005 |
6 | EE | Kazutoshi Kobayashi,
Masao Aramoto,
Yoichi Yuyama,
Akihiko Higuchi,
Hidetoshi Onodera:
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.
ASP-DAC 2005: 619-622 |
5 | EE | Kazutoshi Kobayashi,
Masao Aramoto,
Hidetoshi Onodera:
A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era.
IEICE Transactions 88-C(4): 552-558 (2005) |
2004 |
4 | EE | Yoichi Yuyama,
Masao Aramoto,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
An SoC architecture and its design methodology using unifunctional heterogeneous processor array.
ASP-DAC 2004: 737-742 |
3 | | Yoichi Yuyama,
Masao Aramoto,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
RTL/ISS co-modeling methodology for embedded processor using SystemC.
ISCAS (5) 2004: 305-308 |
2001 |
2 | EE | Kazutoshi Kobayashi,
Makoto Eguchi,
Takuya Iwahashi,
Takehide Shibayama,
Xiang Li,
Kousuke Takai,
Hidetoshi Onodera:
A vector-pipeline DSP for low-rate videophones.
ASP-DAC 2001: 1-2 |
1 | EE | Kazutoshi Kobayashi,
Hidetoshi Onodera:
ST: PERL package for simulation and test environment.
ISCAS (5) 2001: 89-92 |