2009 |
14 | EE | Hiroki Sunagawa,
Haruhiko Terada,
Akira Tsuchiya,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Erect of regularity-enhanced layout on printability and circuit performance of standard cells.
ISQED 2009: 195-200 |
2008 |
13 | EE | Takayuki Fukuoka,
Akira Tsuchiya,
Hidetoshi Onodera:
Statistical gate delay model for Multiple Input Switching.
ASP-DAC 2008: 286-291 |
12 | EE | Yulei Zhang,
Ling Zhang,
Akira Tsuchiya,
Masanori Hashimoto,
Chung-Kuan Cheng:
On-chip high performance signaling using passive compensation.
ICCD 2008: 182-187 |
2007 |
11 | EE | Takeshi Kuboki,
Akira Tsuchiya,
Hidetoshi Onodera:
A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.
ASP-DAC 2007: 120-121 |
10 | EE | Takayuki Fukuoka,
Akira Tsuchiya,
Hidetoshi Onodera:
Worst-case delay analysis considering the variability of transistors and interconnects.
ISPD 2007: 35-42 |
9 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling.
IEICE Transactions 90-C(6): 1267-1273 (2007) |
8 | EE | Takeshi Kuboki,
Akira Tsuchiya,
Hidetoshi Onodera:
Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver.
IEICE Transactions 90-C(6): 1274-1281 (2007) |
2006 |
7 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Interconnect RL extraction at a single representative frequency.
ASP-DAC 2006: 515-520 |
6 | EE | Toshiki Kanamoto,
Tatsuhiko Ikeda,
Akira Tsuchiya,
Hidetoshi Onodera,
Masanori Hashimoto:
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.
IEICE Transactions 89-A(12): 3560-3568 (2006) |
5 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line.
IEICE Transactions 89-A(12): 3585-3593 (2006) |
4 | EE | Yoichi Yuyama,
Akira Tsuchiya,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect.
IEICE Transactions 89-C(3): 327-333 (2006) |
2005 |
3 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Return path selection for loop RL extraction.
ASP-DAC 2005: 1078-1081 |
2 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling.
IEICE Transactions 88-A(4): 885-891 (2005) |
2004 |
1 | EE | Akira Tsuchiya,
Masanori Hashimoto,
Hidetoshi Onodera:
Representative frequency for interconnect R(f)L(f)C extraction.
ASP-DAC 2004: 691-696 |