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Nozomu Togawa

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2008
38EEYouhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: GECOM: Test data compression combined with all unknown response masking. ASP-DAC 2008: 577-582
37EEKazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). ASP-DAC 2008: 697-702
36EEKazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique. IEICE Transactions 91-A(4): 1054-1061 (2008)
35EEYouhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Transactions 91-D(3): 776-780 (2008)
2007
34EEYouhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS 2007: 149-152
33EEKazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Power-efficient LDPC code decoder architecture. ISLPED 2007: 359-362
2006
32EEKazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Memory-Efficient Accelerating Schedule for LDPC Decoder. APCCAS 2006: 1317-1320
31EEShunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ASP-DAC 2006: 594-599
30EEYouhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki: FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC 2006: 653-658
29EEKazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: A parallel LSI architecture for LDPC decoder improving message-passing schedule. ISCAS 2006
28EEKazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. IEICE Transactions 89-A(12): 3602-3612 (2006)
27EEKazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule. IEICE Transactions 89-A(4): 969-978 (2006)
26EEYouhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki: Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Transactions 89-A(4): 996-1004 (2006)
25EEJumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. IEICE Transactions 89-C(3): 243-249 (2006)
2005
24EEKazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Reconfigurable adaptive FEC system with interleaving. ASP-DAC 2005: 1252-1255
23EENaoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A processor core synthesis system in IP-based SoC design. ASP-DAC 2005: 286-291
22EEYouhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura: Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium 2005: 386-389
21EEKazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa: Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. ICCD 2005: 503-510
20EENozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki: Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. ISCAS (4) 2005: 3499-3502
19EEHideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. IEICE Transactions 88-A(4): 876-884 (2005)
18EENozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki: A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Transactions 88-D(7): 1340-1349 (2005)
17EEKazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto: Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving. IEICE Transactions 88-D(7): 1526-1537 (2005)
2004
16EEYuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ASP-DAC 2004: 250-255
15EEJumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: A thread partitioning algorithm in low power high-level synthesis. ASP-DAC 2004: 74-79
14EENozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki: Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC 2004: 743-750
13EEYouhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium 2004: 432-437
2002
12EEYuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. APCCAS (1) 2002: 171-176
11EEJinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: VLSI Architecture for a Flexible Motion Estimation with Parameters. VLSI Design 2002: 452-457
2001
10EEYuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Area/delay estimation for digital signal processor cores. ASP-DAC 2001: 156-161
2000
9EENozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki: An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). ASP-DAC 2000: 309-312
1999
8EENozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki: A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. ASP-DAC 1999: 335-338
7EENozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki: A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. Journal of Circuits, Systems, and Computers 9(1-2): 09-112 (1999)
1998
6 Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki: A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. ASP-DAC 1998: 265-274
5 Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki: An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. ASP-DAC 1998: 519-526
4EENozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 803-818 (1998)
1995
3EENozomu Togawa, Masao Sato, Tatsuo Ohtsuki: Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. ASP-DAC 1995
1994
2EENozomu Togawa, Masao Sato, Tatsuo Ohtsuki: A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. ICCAD 1994: 156-163
1 Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki: A Simultaneous Placement and Global Routing Algorithm for FPGAs. ISCAS 1994: 483-486

Coauthor Index

1Jinku Choi [11] [12]
2Satoshi Goto [17] [21] [24] [27] [28] [29] [32] [33] [36]
3Kayoko Hagi [5]
4Takafumi Hisaki [6]
5Masayuki Ienaga [9]
6Takeshi Ikenaga [17] [21] [24] [27] [28] [29] [32] [33] [36]
7Tatsuyuki Ishikawa [21] [27] [28] [29]
8Yoshiharu Kataoka [10]
9Hideki Kawazu [19] [20]
10Shinji Kimura [13] [22] [26] [30]
11Shunitsu Kohara [23] [31] [37]
12Yuichiro Miyaoka [10] [12] [14] [16] [18] [19] [20] [23] [31]
13Ryuta Nara [37]
14Tatsuo Ohtsuki [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [18] [19] [20] [22] [23] [25] [26] [30] [31] [34] [35] [37] [38]
15Takashi Sakurai [8]
16Masao Sato [1] [2] [3]
17Youhua Shi [13] [22] [26] [30] [34] [35] [37] [38]
18Kazunori Shimizu [17] [21] [24] [27] [28] [29] [32] [33] [36] [37]
19Koichi Tachikake [14] [18]
20Kazuyuki Tanimura [37]
21Naoki Tomono [23] [31]
22Jumpei Uchida [15] [19] [20] [23] [25] [31]
23Kaoru Ukai [7]
24Masao Yanagisawa [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [18] [19] [20] [22] [23] [25] [26] [30] [31] [34] [35] [37] [38]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)