2008 |
38 | EE | Youhua Shi,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
GECOM: Test data compression combined with all unknown response masking.
ASP-DAC 2008: 577-582 |
37 | EE | Kazuyuki Tanimura,
Ryuta Nara,
Shunitsu Kohara,
Kazunori Shimizu,
Youhua Shi,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n).
ASP-DAC 2008: 697-702 |
36 | EE | Kazunori Shimizu,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique.
IEICE Transactions 91-A(4): 1054-1061 (2008) |
35 | EE | Youhua Shi,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A Secure Test Technique for Pipelined Advanced Encryption Standard.
IEICE Transactions 91-D(3): 776-780 (2008) |
2007 |
34 | EE | Youhua Shi,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard.
ISCAS 2007: 149-152 |
33 | EE | Kazunori Shimizu,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Power-efficient LDPC code decoder architecture.
ISLPED 2007: 359-362 |
2006 |
32 | EE | Kazunori Shimizu,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Memory-Efficient Accelerating Schedule for LDPC Decoder.
APCCAS 2006: 1317-1320 |
31 | EE | Shunitsu Kohara,
Naoki Tomono,
Jumpei Uchida,
Yuichiro Miyaoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs.
ASP-DAC 2006: 594-599 |
30 | EE | Youhua Shi,
Nozomu Togawa,
Shinji Kimura,
Masao Yanagisawa,
Tatsuo Ohtsuki:
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction.
ASP-DAC 2006: 653-658 |
29 | EE | Kazunori Shimizu,
Tatsuyuki Ishikawa,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
A parallel LSI architecture for LDPC decoder improving message-passing schedule.
ISCAS 2006 |
28 | EE | Kazunori Shimizu,
Tatsuyuki Ishikawa,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule.
IEICE Transactions 89-A(12): 3602-3612 (2006) |
27 | EE | Kazunori Shimizu,
Tatsuyuki Ishikawa,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule.
IEICE Transactions 89-A(4): 969-978 (2006) |
26 | EE | Youhua Shi,
Nozomu Togawa,
Shinji Kimura,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains.
IEICE Transactions 89-A(4): 996-1004 (2006) |
25 | EE | Jumpei Uchida,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier.
IEICE Transactions 89-C(3): 243-249 (2006) |
2005 |
24 | EE | Kazunori Shimizu,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Reconfigurable adaptive FEC system with interleaving.
ASP-DAC 2005: 1252-1255 |
23 | EE | Naoki Tomono,
Shunitsu Kohara,
Jumpei Uchida,
Yuichiro Miyaoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A processor core synthesis system in IP-based SoC design.
ASP-DAC 2005: 286-291 |
22 | EE | Youhua Shi,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki,
Shinji Kimura:
Low Power Test Compression Technique for Designs with Multiple Scan Chain.
Asian Test Symposium 2005: 386-389 |
21 | EE | Kazunori Shimizu,
Tatsuyuki Ishikawa,
Takeshi Ikenaga,
Satoshi Goto,
Nozomu Togawa:
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm.
ICCD 2005: 503-510 |
20 | EE | Nozomu Togawa,
Hideki Kawazu,
Jumpei Uchida,
Yuichiro Miyaoka,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations.
ISCAS (4) 2005: 3499-3502 |
19 | EE | Hideki Kawazu,
Jumpei Uchida,
Yuichiro Miyaoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis.
IEICE Transactions 88-A(4): 876-884 (2005) |
18 | EE | Nozomu Togawa,
Koichi Tachikake,
Yuichiro Miyaoka,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition.
IEICE Transactions 88-D(7): 1340-1349 (2005) |
17 | EE | Kazunori Shimizu,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving.
IEICE Transactions 88-D(7): 1526-1537 (2005) |
2004 |
16 | EE | Yuichiro Miyaoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A cosynthesis algorithm for application specific processors with heterogeneous datapaths.
ASP-DAC 2004: 250-255 |
15 | EE | Jumpei Uchida,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A thread partitioning algorithm in low power high-level synthesis.
ASP-DAC 2004: 74-79 |
14 | EE | Nozomu Togawa,
Koichi Tachikake,
Yuichiro Miyaoka,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Instruction set and functional unit synthesis for SIMD processor cores.
ASP-DAC 2004: 743-750 |
13 | EE | Youhua Shi,
Shinji Kimura,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test.
Asian Test Symposium 2004: 432-437 |
2002 |
12 | EE | Yuichiro Miyaoka,
Jinku Choi,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.
APCCAS (1) 2002: 171-176 |
11 | EE | Jinku Choi,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
VLSI Architecture for a Flexible Motion Estimation with Parameters.
VLSI Design 2002: 452-457 |
2001 |
10 | EE | Yuichiro Miyaoka,
Yoshiharu Kataoka,
Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Area/delay estimation for digital signal processor cores.
ASP-DAC 2001: 156-161 |
2000 |
9 | EE | Nozomu Togawa,
Masayuki Ienaga,
Masao Yanagisawa,
Tatsuo Ohtsuki:
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper).
ASP-DAC 2000: 309-312 |
1999 |
8 | EE | Nozomu Togawa,
Takashi Sakurai,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing.
ASP-DAC 1999: 335-338 |
7 | EE | Nozomu Togawa,
Kaoru Ukai,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization.
Journal of Circuits, Systems, and Computers 9(1-2): 09-112 (1999) |
1998 |
6 | | Nozomu Togawa,
Takafumi Hisaki,
Masao Yanagisawa,
Tatsuo Ohtsuki:
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs.
ASP-DAC 1998: 265-274 |
5 | | Nozomu Togawa,
Kayoko Hagi,
Masao Yanagisawa,
Tatsuo Ohtsuki:
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays.
ASP-DAC 1998: 519-526 |
4 | EE | Nozomu Togawa,
Masao Yanagisawa,
Tatsuo Ohtsuki:
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 803-818 (1998) |
1995 |
3 | EE | Nozomu Togawa,
Masao Sato,
Tatsuo Ohtsuki:
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization.
ASP-DAC 1995 |
1994 |
2 | EE | Nozomu Togawa,
Masao Sato,
Tatsuo Ohtsuki:
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays.
ICCAD 1994: 156-163 |
1 | | Nozomu Togawa,
Masao Sato,
Tatsuo Ohtsuki:
A Simultaneous Placement and Global Routing Algorithm for FPGAs.
ISCAS 1994: 483-486 |