| 2008 |
|---|
| 9 | EE | Vítor Silva,
Rui Duarte,
Mário P. Véstias,
Horácio C. Neto:
Multiplier-based double precision floating point divider according to the IEEE-754 standard.
ARC 2008: 260-265 |
| 8 | EE | Horácio C. Neto,
Mário P. Véstias:
Decimal multiplier on FPGA using embedded binary multipliers.
FPL 2008: 197-202 |
| 2007 |
|---|
| 7 | EE | Mário P. Véstias,
Horácio C. Neto:
Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems.
FPL 2007: 389-394 |
| 2006 |
|---|
| 6 | EE | Mário P. Véstias,
Horácio C. Neto:
Area/Performance Improvement of NoC Architectures.
ARC 2006: 193-198 |
| 5 | EE | Mário P. Véstias,
Horácio C. Neto:
Co-synthesis of a configurable SoC platform based on a network on chip architecture.
ASP-DAC 2006: 48-53 |
| 4 | EE | Mário P. Véstias,
Horácio C. Neto:
A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation.
FPL 2006: 1-4 |
| 3 | EE | Mário P. Véstias,
Horácio C. Neto:
Area and performance optimization of a generic network-on-chip architecture.
SBCCI 2006: 68-73 |
| 2003 |
|---|
| 2 | EE | Mário P. Véstias,
Horácio C. Neto:
DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures.
SBCCI 2003: 85- |
| 2002 |
|---|
| 1 | EE | Mário P. Véstias,
Horácio C. Neto:
System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures.
IEEE International Workshop on Rapid System Prototyping 2002: 130-137 |
