2008 |
17 | EE | Yiran Chen,
Xiaobin Wang,
Hai Li,
Harry Liu,
Dimitar V. Dimitrov:
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM).
ISQED 2008: 684-690 |
2007 |
16 | EE | Ian W. Marshall,
Mark C. Price,
Hai Li,
Nathan Boyd,
Steve Boult:
Multi-sensor Cross Correlation for Alarm Generation in a Deployed Sensor Network.
EuroSSC 2007: 286-299 |
15 | EE | Weng-Fai Wong,
Cheng-Kok Koh,
Yiran Chen,
Hai Li:
VOSCH: Voltage scaled cache hierarchies.
ICCD 2007: 496-503 |
14 | EE | Hai Li,
Tianming Liu,
Lei Guo,
Stephen T. C. Wong:
Deformable Registration of Dti and Spgr Images.
ISBI 2007: 29-32 |
13 | EE | Yiran Chen,
Hai Li,
Jing Li,
Cheng-Kok Koh:
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.
ISLPED 2007: 195-200 |
12 | EE | Hai Li,
Mark C. Price,
Jonathan Stott,
Ian W. Marshall:
The Development of a Wireless Sensor Network Sensing Node Utilising Adaptive Self-diagnostics.
IWSOS 2007: 30-43 |
2006 |
11 | EE | Hai Li,
Yiran Chen,
Kaushik Roy,
Cheng-Kok Koh:
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.
ASP-DAC 2006: 158-163 |
10 | EE | Hai Li,
Tianming Liu,
Geoffrey Young,
Lei Guo,
Stephen T. C. Wong:
Brain tissue segmentation based on DWI/DTI data.
ISBI 2006: 57-60 |
9 | EE | Hai Li,
Zhenfang Li,
Guisheng Liao,
Zheng Bao:
An estimation method for InSAR interferometric phase combined with image auto-coregistration.
Science in China Series F: Information Sciences 49(3): 386-396 (2006) |
2005 |
8 | EE | Yiran Chen,
Hai Li,
Kaushik Roy,
Cheng-Kok Koh:
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.
ISLPED 2005: 115-118 |
7 | | Hai Li,
Mark Fisher,
Moe Razaz:
Compile-Time Task Scheduling using a Fuzzy Inference System.
Parallel and Distributed Computing and Networks 2005: 546-550 |
6 | EE | Hai Li,
Chen-Yong Cher,
Kaushik Roy,
T. N. Vijaykumar:
Combined circuit and architectural level variable supply-voltage scaling for low power.
IEEE Trans. VLSI Syst. 13(5): 564-576 (2005) |
2004 |
5 | | Hai Li,
Swarup Bhunia,
Yiran Chen,
Kaushik Roy,
T. N. Vijaykumar:
DCG: deterministic clock-gating for low-power microprocessor design.
IEEE Trans. VLSI Syst. 12(3): 245-254 (2004) |
2003 |
4 | EE | Hai Li,
Swarup Bhunia,
Yiran Chen,
T. N. Vijaykumar,
Kaushik Roy:
Deterministic Clock Gating for Microprocessor Power Reduction.
HPCA 2003: 113- |
3 | EE | Hai Li,
Chen-Yong Cher,
T. N. Vijaykumar,
Kaushik Roy:
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power.
MICRO 2003: 19-28 |
2002 |
2 | EE | Swarup Bhunia,
Hai Li,
Kaushik Roy:
A High Performance IDDQ Testable Cache for Scaled CMOS Technologies.
Asian Test Symposium 2002: 157- |
1 | EE | Amit Agarwal,
Hai Li,
Kaushik Roy:
DRG-cache: a data retention gated-ground cache for low power.
DAC 2002: 473-478 |