| 2009 |
|---|
| 10 | EE | Shenghua Liu,
Guoqiang Chen,
Tom Tong Jing,
Lei He,
Tianpei Zhang,
Robi Dutta,
Xian-Long Hong:
Substrate Topological Routing for High-Density Packages.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 207-216 (2009) |
| 2008 |
|---|
| 9 | EE | Shenghua Liu,
Guoqiang Chen,
Tom Tong Jing,
Lei He,
Tianpei Zhang,
Robi Dutta,
Xian-Long Hong:
Topological routing to maximize routability for package substrate.
DAC 2008: 566-569 |
| 8 | EE | Tianpei Zhang,
Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design.
Integration 41(2): 171-182 (2008) |
| 2007 |
|---|
| 7 | EE | Yong Zhan,
Tianpei Zhang,
Sachin S. Sapatnekar:
Module assignment for pin-limited designs under the stacked-Vdd paradigm.
ICCAD 2007: 656-659 |
| 6 | EE | Tianpei Zhang,
Sachin S. Sapatnekar:
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing.
IEEE Trans. VLSI Syst. 15(6): 624-636 (2007) |
| 2006 |
|---|
| 5 | EE | Tianpei Zhang,
Yong Zhan,
Sachin S. Sapatnekar:
Temperature-aware routing in 3D ICs.
ASP-DAC 2006: 309-314 |
| 2005 |
|---|
| 4 | EE | Tianpei Zhang,
Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design.
ASP-DAC 2005: 23-26 |
| 3 | EE | Cristinel Ababei,
Yan Feng,
Brent Goplen,
Hushrav Mogal,
Tianpei Zhang,
Kia Bazargan,
Sachin S. Sapatnekar:
Placement and Routing in 3D Integrated Circuits.
IEEE Design & Test of Computers 22(6): 520-531 (2005) |
| 2004 |
|---|
| 2 | EE | Tianpei Zhang,
Sachin S. Sapatnekar:
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing.
ICCD 2004: 93-98 |
| 2002 |
|---|
| 1 | EE | Tianpei Zhang,
Sachin S. Sapatnekar:
Optimized pin assignment for lower routing congestion after floorplanning phase.
SLIP 2002: 17-21 |
