| 2009 |
|---|
| 150 | EE | Reshma C. Jumani,
Niraj Bharatkumar Jain,
Virendra Singh,
Kewal K. Saluja:
DX-compactor: distributed X-compaction for SoCs.
ACM Great Lakes Symposium on VLSI 2009: 505-510 |
| 149 | EE | Chunhua Yao,
Kewal K. Saluja,
Abhishek A. Sinkar:
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.
VLSI Design 2009: 479-484 |
| 148 | EE | Tai-Lin Chin,
Parameswaran Ramanathan,
Kewal K. Saluja:
Modeling Detection Latency with Collaborative Mobile Sensing Architecture.
IEEE Trans. Computers 58(5): 692-705 (2009) |
| 2008 |
|---|
| 147 | EE | Eric L. Hill,
Mikko H. Lipasti,
Kewal K. Saluja:
An accurate flip-flop selection technique for reducing logic SER.
DSN 2008: 128-136 |
| 146 | EE | Chao Wang,
Parameswaran Ramanathan,
Kewal K. Saluja:
Moments Based Blind Calibration in Mobile Sensor Networks.
ICC 2008: 896-900 |
| 145 | EE | Nidhi Aggarwal,
James E. Smith,
Kewal K. Saluja,
Norman P. Jouppi,
Parthasarathy Ranganathan:
Implementing high availability memory with a duplication cache.
MICRO 2008: 71-82 |
| 144 | EE | Chao Wang,
Parmesh Ramanathan,
Kewal K. Saluja:
Calibrating Nonlinear Mobile Sensors.
SECON 2008: 533-541 |
| 143 | EE | Kewal K. Saluja,
Shriram Vijayakumar,
Warin Sootkaneung,
Xaingning Yang:
NBTI Degradation: A Problem or a Scare?
VLSI Design 2008: 137-142 |
| 142 | EE | Mohammad Gh. Mohammad,
Kewal K. Saluja:
Testing Flash Memories for Tunnel Oxide Defects.
VLSI Design 2008: 157-162 |
| 141 | EE | Yoshinobu Higami,
Kewal K. Saluja,
Hiroshi Takahashi,
Shin-ya Kobayashi,
Yuzo Takamatsu:
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools.
IEICE Transactions 91-D(3): 690-699 (2008) |
| 140 | EE | Xiaoqing Wen,
Kohei Miyase,
Tatsuya Suzuki,
Seiji Kajihara,
Laung-Terng Wang,
Kewal K. Saluja,
Kozo Kinoshita:
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.
J. Electronic Testing 24(4): 379-391 (2008) |
| 2007 |
|---|
| 139 | EE | Xiaoqing Wen,
Kohei Miyase,
Tatsuya Suzuki,
Seiji Kajihara,
Yuji Ohsumi,
Kewal K. Saluja:
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.
DAC 2007: 527-532 |
| 138 | EE | Xiangning Yang,
Kewal K. Saluja:
Combating NBTI Degradation via Gate Sizing.
ISQED 2007: 47-52 |
| 137 | EE | Xiangning Yang,
Eric F. Weglarz,
Kewal K. Saluja:
On NBTI Degradation Process in Digital Logic Circuits.
VLSI Design 2007: 723-730 |
| 136 | EE | Kim T. Le,
Dong Hyun Baik,
Kewal K. Saluja:
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan.
VLSI Design 2007: 769-774 |
| 135 | EE | Yoshinobu Higami,
Kewal K. Saluja,
Hiroshi Takahashi,
Yuzo Takamatsu:
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation.
VLSI Design 2007: 781-786 |
| 134 | EE | Yoshiyuki Nakamura,
Thomas Clouqueur,
Kewal K. Saluja,
Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.
IEEE Trans. VLSI Syst. 15(7): 790-800 (2007) |
| 133 | EE | Masato Nakasato,
Satoshi Ohtake,
Kewal K. Saluja,
Hideo Fujiwara:
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability.
IEICE Transactions 90-D(1): 296-305 (2007) |
| 132 | EE | Xiaoqing Wen,
Seiji Kajihara,
Kohei Miyase,
Tatsuya Suzuki,
Kewal K. Saluja,
Laung-Terng Wang,
Kozo Kinoshita:
A Novel ATPG Method for Capture Power Reduction during Scan Testing.
IEICE Transactions 90-D(9): 1398-1405 (2007) |
| 2006 |
|---|
| 131 | EE | Yoshinobu Higami,
Kewal K. Saluja,
Hiroshi Takahashi,
Shin-ya Kobayashi,
Yuzo Takamatsu:
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits.
ASP-DAC 2006: 659-664 |
| 130 | EE | Tai-Lin Chin,
Parameswaran Ramanathan,
Kewal K. Saluja:
Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles.
GLOBECOM 2006 |
| 129 | EE | Xiaoqing Wen,
Kohei Miyase,
Tatsuya Suzuki,
Yuta Yamato,
Seiji Kajihara,
Laung-Terng Wang,
Kewal K. Saluja:
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.
ICCD 2006 |
| 128 | EE | Tai-Lin Chin,
Parameswaran Ramanathan,
Kewal K. Saluja:
Analytic modeling of detection latency in mobile sensor networks.
IPSN 2006: 194-201 |
| 127 | EE | Dong Hyun Baik,
Kewal K. Saluja:
Test Cost Reduction Using Partitioned Grid Random Access Scan.
VLSI Design 2006: 169-174 |
| 126 | EE | Xiaoqing Wen,
Seiji Kajihara,
Kohei Miyase,
Tatsuya Suzuki,
Kewal K. Saluja,
Laung-Terng Wang,
Khader S. Abdel-Hafez,
Kozo Kinoshita:
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.
VTS 2006: 58-65 |
| 125 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.
IEEE Trans. VLSI Syst. 14(11): 1203-1215 (2006) |
| 124 | EE | Xiaoqing Wen,
Seiji Kajihara,
Kohei Miyase,
Yuta Yamato,
Kewal K. Saluja,
Laung-Terng Wang,
Kozo Kinoshita:
A Per-Test Fault Diagnosis Method Based on the X-Fault Model.
IEICE Transactions 89-D(11): 2756-2765 (2006) |
| 123 | EE | Yoshiyuki Nakamura,
Thomas Clouqueur,
Kewal K. Saluja,
Hideo Fujiwara:
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch.
IEICE Transactions 89-D(3): 1165-1172 (2006) |
| 122 | EE | Xiaoqing Wen,
Yoshiyuki Yamashita,
Seiji Kajihara,
Laung-Terng Wang,
Kewal K. Saluja,
Kozo Kinoshita:
A New Method for Low-Capture-Power Test Generation for Scan Testing.
IEICE Transactions 89-D(5): 1679-1686 (2006) |
| 121 | EE | Tai-Lin Chin,
Thomas Clouqueur,
Parameswaran Ramanathan,
Kewal K. Saluja:
Vulnerability of Surveillance Networks to Faults.
IJDSN 2(3): 289-311 (2006) |
| 120 | EE | Eric F. Weglarz,
Kewal K. Saluja,
Mikko H. Lipasti:
Energy Estimation of the Memory Subsystem in Multiprocessor Systems.
J. Low Power Electronics 2(3): 325-332 (2006) |
| 2005 |
|---|
| 119 | EE | Thomas Clouqueur,
Hideo Fujiwara,
Kewal K. Saluja:
A Class of Linear Space Compactors for Enhanced Diagnostic.
Asian Test Symposium 2005: 260-265 |
| 118 | EE | Dong Hyun Baik,
Kewal K. Saluja:
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size.
Asian Test Symposium 2005: 272-277 |
| 117 | | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Testing Superscalar Processors in Functional Mode.
FPL 2005: 747-750 |
| 116 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Instruction-based delay fault self-testing of pipelined processor cores.
ISCAS (6) 2005: 5686-5689 |
| 115 | EE | Jeng-Liang Tsai,
Dong Hyun Baik,
Charlie Chung-Ping Chen,
Kewal K. Saluja:
False Path and Clock Scheduling Based Yield-Aware Gate Sizing.
VLSI Design 2005: 423-426 |
| 114 | EE | Marong Phadoongsidhi,
Kewal K. Saluja:
SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits.
VLSI Design 2005: 820-823 |
| 113 | EE | Xiaoqing Wen,
Yoshiyuki Yamashita,
Seiji Kajihara,
Laung-Terng Wang,
Kewal K. Saluja,
Kozo Kinoshita:
On Low-Capture-Power Test Generation for Scan Testing.
VTS 2005: 265-270 |
| 112 | EE | Jeng-Liang Tsai,
Dong Hyun Baik,
Charlie Chung-Ping Chen,
Kewal K. Saluja:
Yield-Driven, False-Path-Aware Clock Skew Scheduling.
IEEE Design & Test of Computers 22(3): 214-222 (2005) |
| 111 | EE | Hiroshi Takahashi,
Keith J. Keller,
Kim T. Le,
Kewal K. Saluja,
Yuzo Takamatsu:
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 252-263 (2005) |
| 110 | EE | Mohammad Gh. Mohammad,
Kewal K. Saluja:
Optimizing program disturb fault tests using defect-based testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 905-915 (2005) |
| 109 | EE | Yong Chang Kim,
Vishwani D. Agrawal,
Kewal K. Saluja:
Combinational automatic test pattern generation for acyclic sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 948-956 (2005) |
| 108 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Delay Fault Testing of Processor Cores in Functional Mode.
IEICE Transactions 88-D(3): 610-618 (2005) |
| 107 | EE | Xiaoqing Wen,
Seiji Kajihara,
Hideo Tamamoto,
Kewal K. Saluja,
Kozo Kinoshita:
On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.
IEICE Transactions 88-D(4): 703-710 (2005) |
| 106 | EE | Xiaoqing Wen,
Hideo Tamamoto,
Kewal K. Saluja,
Kozo Kinoshita:
Fault Diagnosis of Physical Defects Using Unknown Behavior Model.
J. Comput. Sci. Technol. 20(2): 187-194 (2005) |
| 105 | EE | Xiaoqing Wen,
Tatsuya Suzuki,
Seiji Kajihara,
Kohei Miyase,
Yoshihiro Minamoto,
Laung-Terng Wang,
Kewal K. Saluja:
Efficient Test Set Modification for Capture Power Reduction.
J. Low Power Electronics 1(3): 319-330 (2005) |
| 2004 |
|---|
| 104 | EE | Jeng-Liang Tsai,
Dong Hyun Baik,
Charlie Chung-Ping Chen,
Kewal K. Saluja:
A yield improvement methodology using pre- and post-silicon statistical clock scheduling.
ICCAD 2004: 611-618 |
| 103 | EE | Xiaoqing Wen,
Tokiharu Miyoshi,
Seiji Kajihara,
Laung-Terng Wang,
Kewal K. Saluja,
Kozo Kinoshita:
On per-test fault diagnosis using the X-fault model.
ICCAD 2004: 633-640 |
| 102 | EE | Eric F. Weglarz,
Kewal K. Saluja,
T. M. Mak:
Testing of Hard Faults in Simultaneous Multithreaded Processors.
IOLTS 2004: 95-100 |
| 101 | EE | Matthew L. King,
Kewal K. Saluja:
Testing Micropipelined Asynchronous Circuits.
ITC 2004: 329-338 |
| 100 | EE | Marong Phadoongsidhi,
Kewal K. Saluja:
Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults.
VLSI Design 2004: 437-442 |
| 99 | EE | Dong Hyun Baik,
Kewal K. Saluja,
Seiji Kajihara:
Random Access Scan: A solution to test power, test data volume and test time.
VLSI Design 2004: 883-888 |
| 98 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Instruction-Based Delay Fault Self-Testing of Processor Cores.
VLSI Design 2004: 933- |
| 97 | EE | Thomas Clouqueur,
Kewal K. Saluja,
Parameswaran Ramanathan:
Fault Tolerance in Collaborative Sensor Networks for Target Detection.
IEEE Trans. Computers 53(3): 320-333 (2004) |
| 2003 |
|---|
| 96 | EE | Kewal K. Saluja:
Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits.
Asian Test Symposium 2003: 2 |
| 95 | EE | Xiaoqing Wen,
Hideo Tamamoto,
Kewal K. Saluja,
Kozo Kinoshita:
Fault Diagnosis for Physical Defects of Unknown Behaviors.
Asian Test Symposium 2003: 236-241 |
| 94 | EE | Mohammad Gh. Mohammad,
Kewal K. Saluja:
Stress Test for Disturb Faults in Non-Volatile Memories.
Asian Test Symposium 2003: 384-389 |
| 93 | EE | Virendra Singh,
Michiko Inoue,
Kewal K. Saluja,
Hideo Fujiwara:
Software-Based Delay Fault Testing of Processor Cores.
Asian Test Symposium 2003: 68-71 |
| 92 | EE | Marong Phadoongsidhi,
Kewal K. Saluja:
Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits.
ICCD 2003: 42-47 |
| 91 | EE | Vishwani D. Agrawal,
Dong Hyun Baik,
Yong Chang Kim,
Kewal K. Saluja:
Exclusive Test and its Applications to Fault Diagnosis.
VLSI Design 2003: 143-148 |
| 90 | EE | Mohammad Gh. Mohammad,
Kewal K. Saluja:
Electrical Model For Program Disturb Faults in Non-Volatile Memories.
VLSI Design 2003: 217-222 |
| 89 | EE | Thomas Clouqueur,
Veradej Phipatanasuphorn,
Parameswaran Ramanathan,
Kewal K. Saluja:
Sensor Deployment Strategy for Detection of Targets Traversing a Region.
MONET 8(4): 453-461 (2003) |
| 2002 |
|---|
| 88 | EE | Marong Phadoongsidhi,
Kim T. Le,
Kewal K. Saluja:
A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits.
Asian Test Symposium 2002: 182- |
| 87 | EE | Keith J. Keller,
Hiroshi Takahashi,
Kim T. Le,
Kewal K. Saluja,
Yuzo Takamatsu:
Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints.
Asian Test Symposium 2002: 242-247 |
| 86 | EE | Hiroshi Takahashi,
Kewal K. Saluja,
Yuzo Takamatsu:
An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets.
PRDC 2002: 275-282 |
| 85 | EE | Eric F. Weglarz,
Kewal K. Saluja,
Mikko H. Lipasti:
Minimizing Energy Consumption for High-Performance Processing.
VLSI Design 2002: 199- |
| 84 | EE | Fei Li,
Lei He,
Kewal K. Saluja:
Estimation of Maximum Power-Up Current.
VLSI Design 2002: 51- |
| 83 | EE | Yong Chang Kim,
Vishwani D. Agrawal,
Kewal K. Saluja:
Multiple Faults: Modeling, Simulation and Test.
VLSI Design 2002: 592-597 |
| 82 | EE | Thomas Clouqueur,
Veradej Phipatanasuphorn,
Parameswaran Ramanathan,
Kewal K. Saluja:
Sensor deployment strategy for target detection.
WSNA 2002: 42-48 |
| 81 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Kewal K. Saluja,
Yuzo Takamatsu:
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 362-368 (2002) |
| 2001 |
|---|
| 80 | EE | Hiroshi Takahashi,
Marong Phadoongsidhi,
Yoshinobu Higami,
Kewal K. Saluja,
Yuzo Takamatsu:
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits.
Asian Test Symposium 2001: 63- |
| 79 | | Yong Chang Kim,
Vishwani D. Agrawal,
Kewal K. Saluja:
Combinational test generation for various classes of acyclic sequential circuits.
ITC 2001: 1078-1087 |
| 78 | | Keith J. Keller,
Hiroshi Takahashi,
Kewal K. Saluja,
Yuzo Takamatsu:
On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits.
ITC 2001: 568-577 |
| 77 | EE | Yong Chang Kim,
Kewal K. Saluja,
Vishwani D. Agrawal:
Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.
VLSI Design 2001: 143-148 |
| 76 | EE | Thomas Clouqueur,
Ozen Ercevik,
Kewal K. Saluja,
Hiroshi Takahashi:
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows.
VLSI Design 2001: 391-396 |
| 75 | EE | Mohammad Gh. Mohammad,
Kewal K. Saluja:
Flash Memory Disturbances: Modeling and Test.
VTS 2001: 218-224 |
| 74 | EE | Richard M. Chou,
Kewal K. Saluja:
Testable Sequential Circuit Design: A Partition and Resynthesis Approach.
VTS 2001: 62-67 |
| 73 | EE | Mohammad Gh. Mohammad,
Kewal K. Saluja,
Alex S. Yap:
Fault Models and Test Procedures for Flash Memory Disturbances.
J. Electronic Testing 17(6): 495-508 (2001) |
| 2000 |
|---|
| 72 | EE | Yoshinobu Higami,
Yuzo Takamatsu,
Kewal K. Saluja,
Kozo Kinoshita:
Fault models and test generation for IDDQ testing: embedded tutorial.
ASP-DAC 2000: 509-514 |
| 71 | EE | Faisal Rashid,
Kewal K. Saluja,
Parameswaran Ramanathan:
Fault Tolerance through Re-Execution in Multiscalar Architecture.
DSN 2000: 482-491 |
| 70 | EE | Hiroki Wada,
Toshimitsu Masuzawa,
Kewal K. Saluja,
Hideo Fujiwara:
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency.
VLSI Design 2000: 300-305 |
| 69 | EE | Mohammad Gh. Mohammad,
Kewal K. Saluja,
Alex S. Yap:
Testing Flash Memories.
VLSI Design 2000: 406-411 |
| 68 | EE | Yoshinobu Higami,
Yuzo Takamatsu,
Kewal K. Saluja,
Kozo Kinoshita:
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.
J. Electronic Testing 16(5): 443-451 (2000) |
| 67 | EE | Yoshinobu Higami,
Kewal K. Saluja,
Yuzo Takamatsu,
Kozo Kinoshita:
Static test compaction for IDDQ testing of bridging faults in sequential circuits.
Systems and Computers in Japan 31(11): 41-50 (2000) |
| 1999 |
|---|
| 66 | EE | Yoshinobu Higami,
Yuzo Takamatsu,
Kewal K. Saluja,
Kozo Kinoshita:
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.
Asian Test Symposium 1999: 141-146 |
| 65 | EE | Yong Chang Kim,
Kewal K. Saluja,
Vishwani D. Agrawal:
A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability.
Great Lakes Symposium on VLSI 1999: 300- |
| 64 | | Yoshinobu Higami,
Kewal K. Saluja,
Kozo Kinoshita:
Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits.
VLSI Design 1999: 72-77 |
| 1998 |
|---|
| 63 | EE | Xiaoqing Wen,
Tooru Honzawa,
Hideo Tamamoto,
Kewal K. Saluja,
Kozo Kinoshita:
Design for Diagnosability of CMOS Circuits.
Asian Test Symposium 1998: 144-149 |
| 62 | EE | Yoshinobu Higami,
Kewal K. Saluja,
Kozo Kinoshita:
Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.
Asian Test Symposium 1998: 312-317 |
| 61 | EE | Seiji Kajihara,
Kewal K. Saluja:
On Test Pattern Compaction Using Random Pattern Fault Simulation.
VLSI Design 1998: 464-469 |
| 60 | | Lama Nachman,
Kewal K. Saluja,
Shambhu J. Upadhyaya,
Robert Reuse:
A Novel Approach to Random Pattern Testing of Sequential Circuits.
IEEE Trans. Computers 47(1): 129-134 (1998) |
| 59 | EE | Yong Chang Kim,
Kewal K. Saluja:
Sequential test generators: past, present and future.
Integration 26(1-2): 41-54 (1998) |
| 58 | EE | Kim T. Le,
Kewal K. Saluja:
A Heuristic Measure to Maximize Detected Faults per Test.
J. Electronic Testing 13(1): 57-60 (1998) |
| 1997 |
|---|
| 57 | EE | Richard M. Chou,
Kewal K. Saluja:
Sequential Circuit Testing: From DFT to SFT.
VLSI Design 1997: 274-278 |
| 56 | EE | Richard M. Chou,
Kewal K. Saluja,
Vishwani D. Agrawal:
Scheduling tests for VLSI systems under power constraints.
IEEE Trans. VLSI Syst. 5(2): 175-185 (1997) |
| 55 | EE | K.-T. Cheng,
Kewal K. Saluja,
Hans-Joachim Wunderlich:
Guest Editorial.
J. Electronic Testing 11(1): 7-8 (1997) |
| 1996 |
|---|
| 54 | | Lama Nachman,
Kewal K. Saluja,
Shambhu J. Upadhyaya,
Robert Reuse:
Random Pattern Testing for Sequential Circuits Revisited.
FTCS 1996: 44-52 |
| 53 | EE | Xiaoqing Wen,
Kewal K. Saluja:
A new method towards achieving global optimality in technology mapping.
ICCAD 1996: 9-12 |
| 52 | EE | Timothy John Lambert,
Kewal K. Saluja:
Methods for Dynamic Test Vector compaction in Sequential Test Generation.
VLSI Design 1996: 166-169 |
| 51 | EE | Ashutosh Mujumdar,
Rajiv Jain,
Kewal K. Saluja:
Incorporating performance and testability constraints during binding in high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1212-1225 (1996) |
| 50 | EE | Manoj Franklin,
Kewal K. Saluja:
Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1081-1087 (1996) |
| 1995 |
|---|
| 49 | | Ning Jiang,
Richard M. Chou,
Kewal K. Saluja:
Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan.
FTCS 1995: 41-49 |
| 48 | EE | Hao Zheng,
Kewal K. Saluja,
Rajiv Jain:
Test application time reduction for scan based sequential circuits.
Great Lakes Symposium on VLSI 1995: 188-191 |
| 47 | EE | Manoj Franklin,
Kewal K. Saluja,
Kyuchull Kim:
Fast computation of MISR signatures.
VLSI Design 1995: 414-418 |
| 46 | EE | Ting-Yu Kuo,
Chun-Yeh Liu,
Kewal K. Saluja:
An optimized testable architecture for finite state machines.
VTS 1995: 164-169 |
| 45 | EE | Soo Young Lee,
Kewal K. Saluja:
Test application time reduction for sequential circuits with scan.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1128-1140 (1995) |
| 1994 |
|---|
| 44 | | Ashutosh Mujumdar,
Rajiv Jain,
Kewal K. Saluja:
Behavioral Synthesis of Testable Designs.
FTCS 1994: 436-445 |
| 43 | | Richard M. Chou,
Kewal K. Saluja,
Vishwani D. Agrawal:
Power Constraint Scheduling of Tests.
VLSI Design 1994: 271-274 |
| 42 | | Manoj Franklin,
Kewal K. Saluja:
An Algorithm to Test Reconfigured RAMs.
VLSI Design 1994: 359-364 |
| 41 | | Manoj Franklin,
Kewal K. Saluja:
Hypergraph Coloring and Reconfigured RAM Testing.
IEEE Trans. Computers 43(6): 725-736 (1994) |
| 40 | EE | Ashutosh Mujumdar,
Rajiv Jain,
Kewal K. Saluja:
Incorporating testability considerations in high-level synthesis.
J. Electronic Testing 5(1): 43-55 (1994) |
| 39 | EE | Kewal K. Saluja:
On-chip testing of random access memories.
J. Electronic Testing 5(4): 367-376 (1994) |
| 1993 |
|---|
| 38 | | Soo Young Lee,
Kewal K. Saluja:
Efficient Test Vectors for ISCAS Sequential Benchmark Circuits.
ISCAS 1993: 1511-1514 |
| 37 | EE | Vishwani D. Agrawal,
Charles R. Kime,
Kewal K. Saluja:
A Tutorial on Built-in Self-Test. I. Principles.
IEEE Design & Test of Computers 10(1): 73-82 (1993) |
| 36 | EE | Vishwani D. Agrawal,
Charles R. Kime,
Kewal K. Saluja:
A Tutorial on Built-In Self-Test, Part 2: Applications.
IEEE Design & Test of Computers 10(2): 69-77 (1993) |
| 35 | | Todd P. Kelsey,
Kewal K. Saluja,
Soo Young Lee:
An Efficient Algorithm for Sequential Circuit Test Generation.
IEEE Trans. Computers 42(11): 1361-1371 (1993) |
| 34 | EE | Chun-Yeh Liu,
Kewal K. Saluja:
An efficient algorithm for bipartite PLA folding.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1839-1847 (1993) |
| 1992 |
|---|
| 33 | | Ashutosh Mujumdar,
Kewal K. Saluja,
Rajiv Jain:
Incorporating Testability Considerations in High-Level Systhesis.
FTCS 1992: 272-279 |
| 32 | EE | Soo Young Lee,
Kewal K. Saluja:
An algorithm to reduce test application time in full scan designs.
ICCAD 1992: 17-20 |
| 31 | EE | Kewal K. Saluja,
Chin-Foo See:
An Efficient Signature Computation Method.
IEEE Design & Test of Computers 9(4): 22-26 (1992) |
| 1991 |
|---|
| 30 | | Manoj Franklin,
Kewal K. Saluja:
Pattern Sensitive Fault Testing of RAMs with Bullt-in ECC.
FTCS 1991: 385-392 |
| 29 | | Manoj Franklin,
Kewal K. Saluja:
An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults.
ITC 1991: 675-684 |
| 28 | EE | Keiho Akiyama,
Kewal K. Saluja:
A method of reducing aliasing in a built-in self-test environment.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 548-553 (1991) |
| 1990 |
|---|
| 27 | | Manoj Franklin,
Kewal K. Saluja:
Built-in Self-testing of Random-Access Memories.
IEEE Computer 23(10): 45-56 (1990) |
| 26 | EE | Kewal K. Saluja,
Kyuchull Kim:
Improved Test Generation for High-Activity Circuits.
IEEE Design & Test of Computers 7(4): 26-31 (1990) |
| 25 | | Kifung C. Cheung,
Gurindar S. Sohi,
Kewal K. Saluja,
Dhiraj K. Pradhan:
Design and Analysis of a Gracefully Degrading Interleaved Memory System.
IEEE Trans. Computers 39(1): 63-71 (1990) |
| 1989 |
|---|
| 24 | | Manoj Franklin,
Kewal K. Saluja,
Kozo Kinoshita:
Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability.
ITC 1989: 327-336 |
| 1988 |
|---|
| 23 | | Gary L. Craig,
Charles R. Kime,
Kewal K. Saluja:
Test Scheduling and Control for VLSI Built-In Self-Test.
IEEE Trans. Computers 37(9): 1099-1109 (1988) |
| 22 | | Sudhakar M. Reddy,
Kewal K. Saluja,
Mark G. Karpovsky:
A Data Compression Technique for Built-In Self-Test.
IEEE Trans. Computers 37(9): 1151-1156 (1988) |
| 21 | EE | Shambhu J. Upadhyaya,
Kewal K. Saluja:
A new approach to the design of built-in self-testing PLAs for high fault coverage.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 60-67 (1988) |
| 20 | EE | Kewal K. Saluja,
Rajiv Sharma,
Charles R. Kime:
A concurrent testing technique for digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(12): 1250-1260 (1988) |
| 1987 |
|---|
| 19 | EE | Chun-Yeh Liu,
Kewal K. Saluja,
Shambhu J. Upadhyaya:
BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays.
DAC 1987: 385-391 |
| 18 | EE | Kifung C. Cheung,
Gurindar S. Sohi,
Kewal K. Saluja,
Dhiraj K. Pradhan:
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System.
ISCA 1987: 224-231 |
| 1986 |
|---|
| 17 | | Kim T. Le,
Kewal K. Saluja:
A Novel Approach for Testing Memories Using a Built-In Self Testing Technique.
ITC 1986: 830-839 |
| 16 | | Kozo Kinoshita,
Kewal K. Saluja:
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme.
IEEE Trans. Computers 35(10): 862-870 (1986) |
| 15 | | Kewal K. Saluja,
Ramaswami Dandapani:
An Alternative to Scan Design Methods for Sequential Machines.
IEEE Trans. Computers 35(4): 384-388 (1986) |
| 14 | | Kewal K. Saluja,
Ramaswami Dandapani:
Testable Design of Single-Output Sequential Machines Using Checking Experiments.
IEEE Trans. Computers 35(7): 658-662 (1986) |
| 13 | | Shambhu J. Upadhyaya,
Kewal K. Saluja:
A Wachtdog Processor Based General Rollback Technique with Multiple Retries.
IEEE Trans. Software Eng. 12(1): 87-95 (1986) |
| 1985 |
|---|
| 12 | | Hideo Fujiwara,
Kewal K. Saluja,
Kozo Kinoshita:
A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead.
ITC 1985: 574-582 |
| 11 | | C. Boswell,
Kewal K. Saluja,
Kozo Kinoshita:
Design of Programmable Logic Arrays for Parallel Testing.
Comput. Syst. Sci. Eng. 1(1): 5-16 (1985) |
| 10 | | Kewal K. Saluja,
Kozo Kinoshita:
Test Pattern Generation for API Faults in RAM.
IEEE Trans. Computers 34(3): 284-287 (1985) |
| 1984 |
|---|
| 9 | | Kozo Kinoshita,
Kewal K. Saluja:
Built-in Testing of Memory Using On-chip Compact Testing Scheme.
ITC 1984: 271-281 |
| 1983 |
|---|
| 8 | | Kewal K. Saluja,
Li Shen,
Stephen Y. H. Su:
A Simplified Algorithm for Testing Microprocessors.
ITC 1983: 668-675 |
| 7 | | Kewal K. Saluja,
Mark G. Karpovsky:
Testing Computer Hardware through Data Compression in Space and Time.
ITC 1983: 83-88 |
| 6 | | Kewal K. Saluja,
Kozo Kinoshita,
Hideo Fujiwara:
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.
IEEE Trans. Computers 32(11): 1038-1046 (1983) |
| 1980 |
|---|
| 5 | | Kewal K. Saluja:
Synchronous Sequential Machines: A Modular and Testable Design.
IEEE Trans. Computers 29(11): 1020-1025 (1980) |
| 4 | EE | Kewal K. Saluja,
Brian D. O. Anderson:
Fault diagnosis in loop-connected systems.
Inf. Sci. 21(1): 75-92 (1980) |
| 1979 |
|---|
| 3 | | Kewal K. Saluja,
E. H. Ong:
Minimization of Reed-Muller Canonic Expansion.
IEEE Trans. Computers 28(7): 535-537 (1979) |
| 1975 |
|---|
| 2 | | Kewal K. Saluja,
Sudhakar M. Reddy:
Fault Detecting Test Sets for Reed-Muller Canonic Networks.
IEEE Trans. Computers 24(10): 995-998 (1975) |
| 1972 |
|---|
| 1 | | Kewal K. Saluja,
Sudhakar M. Reddy:
Multiple Faults in Reed-Muller Canonic Networks
FOCS 1972: 185-191 |
