2008 |
12 | EE | Dan Bailey,
Eric Soenen,
Puneet Gupta,
Paul G. Villarrubia,
Sang H. Dhong:
Challenges at 45nm and beyond.
ICCAD 2008: 7 |
2007 |
11 | EE | Brian K. Flachs,
Shigehiro Asano,
Sang H. Dhong,
H. Peter Hofstee,
Gilles Gervais,
Roy Kim,
Tien Le,
Peichun Liu,
Jens Leenstra,
John S. Liberty,
Brad W. Michael,
Hwa-Joon Oh,
Silvia M. Müller,
Osamu Takahashi,
Koji Hirairi,
Atsushi Kawasumi,
Hiroaki Murakami,
Hiromi Noro,
Shoji Onishi,
Juergen Pille,
Joel Silberman,
Suksoon Yong,
Akiyuki Hatakeyama,
Yukio Watanabe,
Naoka Yano,
Daniel A. Brokenshire,
Mohammad Peyravian,
VanDung To,
Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.
IBM Journal of Research and Development 51(5): 529-544 (2007) |
2006 |
10 | EE | Rajat Chaudhry,
Daniel L. Stasiak,
Stephen D. Posluszny,
Sang H. Dhong:
A cycle accurate power estimation tool.
ASP-DAC 2006: 867-870 |
2005 |
9 | | Osamu Takahashi,
Russ Cook,
Scott R. Cottier,
Sang H. Dhong,
Brian K. Flachs,
Koji Hirairi,
Atsushi Kawasumi,
Hiroaki Murakami,
Hiromi Noro,
Hwa-Joon Oh,
S. Onish,
Juergen Pille,
Joel Silberman:
The circuit design of the synergistic processor element of a CELL processor.
ICCAD 2005: 111-117 |
8 | EE | Silvia M. Müller,
Christian Jacobi,
Hwa-Joon Oh,
Kevin D. Tran,
Scott R. Cottier,
Brad W. Michael,
Hiroo Nishikawa,
Yonetaro Totsuka,
Tatsuya Namatame,
Naoka Yano,
Takashi Machida,
Sang H. Dhong:
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor.
IEEE Symposium on Computer Arithmetic 2005: 59-67 |
7 | EE | Osamu Takahashi,
Scott R. Cottier,
Sang H. Dhong,
Brian K. Flachs,
Joel Silberman:
Power-Conscious Design of the Cell Processor's Synergistic Processor Element.
IEEE Micro 25(5): 10-18 (2005) |
6 | EE | Toru Asano,
Joel Silberman,
Sang H. Dhong,
Osamu Takahashi,
Michael White,
Scott R. Cottier,
Takaaki Nakazato,
Atsushi Kawasumi,
Hiroshi Yoshihara:
Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.
IEEE Micro 25(5): 30-38 (2005) |
2000 |
5 | EE | Stephen D. Posluszny,
N. Aoki,
David Boerstler,
P. Coulman,
Sang H. Dhong,
Brian K. Flachs,
H. Peter Hofstee,
N. Kojima,
Ohsang Kwon,
K. Lee,
D. Meltzer,
Kevin J. Nowka,
J. Park,
J. Peter,
Joel Silberman,
Osamu Takahashi,
Paul Villarrubia:
"Timing closure by design, " a high frequency microprocessor design methodology.
DAC 2000: 712-717 |
4 | EE | David H. Allen,
Sang H. Dhong,
H. Peter Hofstee,
Jens Leenstra,
Kevin J. Nowka,
Daniel L. Stasiak,
Dieter F. Wendel:
Custom circuit design as a driver of microprocessor performance.
IBM Journal of Research and Development 44(6): 799-822 (2000) |
1998 |
3 | EE | David F. Heidel,
Sang H. Dhong,
H. Peter Hofstee,
Michael Immediato,
Kevin J. Nowka,
Joel Silberman,
Kevin G. Stawiasz:
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor.
VTS 1998: 234-238 |
1995 |
2 | | Sang H. Dhong,
Masahiro Tanaka,
Steven W. Tomashot,
Toshiaki Kirihata:
A low-noise TTL-compatible CMOS off-chip driver circuit.
IBM Journal of Research and Development 39(1-2): 105-112 (1995) |
1 | | Toshio Sunaga,
Koji Hosokawa,
Sang H. Dhong,
Koji Kitamura:
A 64Kb - 32 DRAM for graphics applications.
IBM Journal of Research and Development 39(1-2): 43-50 (1995) |