2007 | ||
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33 | EE | Makoto Nagata: On-Chip Measurements Complementary to Design Flow for Integrity in SoCs. DAC 2007: 400-403 |
32 | EE | Koichiro Noguchi, Makoto Nagata: An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. IEEE Trans. VLSI Syst. 15(10): 1101-1110 (2007) |
31 | EE | Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata: Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. IEICE Transactions 90-A(12): 2651-2660 (2007) |
30 | EE | Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata: Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits. IEICE Transactions 90-A(2): 380-387 (2007) |
29 | EE | Masao Morimoto, Makoto Nagata, Kazuo Taki: Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations. IEICE Transactions 90-C(4): 675-682 (2007) |
28 | EE | Yoshihide Komatsu, Koichiro Ishibashi, Makoto Nagata: Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias. IEICE Transactions 90-C(4): 692-698 (2007) |
27 | EE | Koichiro Noguchi, Takushi Hashida, Makoto Nagata: On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration. IEICE Transactions 90-C(6): 1189-1196 (2007) |
26 | EE | Kouji Ichikawa, Yuki Takahashi, Makoto Nagata: Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements. IEICE Transactions 90-C(6): 1282-1290 (2007) |
25 | EE | Yohei Fukumizu, Naoki Gochi, Makoto Nagata, Kazuo Taki: A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System. IEICE Transactions 90-C(6): 1299-1303 (2007) |
2006 | ||
24 | EE | Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki: A built-in power supply noise probe for digital LSIs. ASP-DAC 2006: 106-107 |
23 | EE | Daisuke Kosaka, Makoto Nagata: Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation. ASP-DAC 2006: 677-682 |
22 | EE | Yohei Fukumizu, Shuji Ohno, Makoto Nagata, Kazuo Taki: Communication Scheme for a Highly Collision-Resistive RFID System. IEICE Transactions 89-A(2): 408-415 (2006) |
21 | EE | Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa: An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. IEICE Transactions 89-C(11): 1535-1543 (2006) |
20 | EE | Mitsuya Fukazawa, Makoto Nagata: Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise. IEICE Transactions 89-C(11): 1559-1566 (2006) |
19 | EE | Yohei Fukumizu, Makoto Nagata, Kazuo Taki: Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach. IEICE Transactions 89-C(11): 1581-1590 (2006) |
18 | EE | Yuuichirou Ikeda, Masaya Sumita, Makoto Nagata: Multi-Ported Register File for Reducing the Impact of PVT Variation. IEICE Transactions 89-C(3): 356-363 (2006) |
17 | EE | Koichiro Noguchi, Makoto Nagata: An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity. IEICE Transactions 89-C(6): 761-768 (2006) |
2005 | ||
16 | EE | Koichiro Noguchi, Makoto Nagata: On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits. DATE 2005: 146-151 |
15 | EE | Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki: Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition. IEICE Transactions 88-A(12): 3324-3331 (2005) |
14 | EE | Masao Morimoto, Makoto Nagata, Kazuo Taki: High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition. IEICE Transactions 88-C(10): 2001-2008 (2005) |
13 | EE | Kenji Shimazaki, Makoto Nagata, Takeshi Okumoto, Shozo Hirano, Hiroyuki Tsujikawa: Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits. IEICE Transactions 88-C(4): 589-596 (2005) |
2002 | ||
12 | EE | Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata: A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) 2002: 197-200 |
11 | EE | Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata: Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. VLSI Design 2002: 71-76 |
2001 | ||
10 | EE | Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata: Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC 2001: 13-14 |
9 | EE | Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata: Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED 2001: 482-487 |
8 | EE | Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata: An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS 2001: 1115-1122 |
2000 | ||
7 | EE | Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata: A smart imager for the vision processing front-END. ASP-DAC 2000: 19-20 |
6 | EE | Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata: An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC 2000: 23-24 |
5 | EE | Makoto Nagata, Atsushi Iwata: Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. ASP-DAC 2000: 623-630 |
4 | EE | Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata: Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 671-678 (2000) |
1999 | ||
3 | Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie: A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI 1999: 77-88 | |
1998 | ||
2 | Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata: Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP 1998: 582-585 | |
1 | Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata: Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP 1998: 586-589 |