2009 |
17 | EE | Lei Zhao,
Hui Xu,
Naomi Seki,
Saito Yoshiki,
Yohei Hasegawa,
Kimiyoshi Usami,
Hideharu Amano:
Cache Controller Design on Ultra Low Leakage Embedded Processors.
ARCS 2009: 171-182 |
16 | EE | Kimiyoshi Usami,
Toshiaki Shirai,
Tasunori Hashida,
Hiroki Masuda,
Seidai Takeda,
Mitsutaka Nakata,
Naomi Seki,
Hideharu Amano,
Mitaro Namiki,
Masashi Imai,
Masaaki Kondo,
Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.
VLSI Design 2009: 381-386 |
2008 |
15 | EE | Jerry Frenkil,
Ken Choi,
Kimiyoshi Usami:
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis.
DATE 2008 |
14 | EE | Naomi Seki,
Lei Zhao,
Jo Kei,
Daisuke Ikebuchi,
Yu Kojima,
Yohei Hasegawa,
Hideharu Amano,
Toshihiro Kashima,
Seidai Takeda,
Toshiaki Shirai,
Mitsutaka Nakata,
Kimiyoshi Usami,
Tetsuya Sunata,
Jun Kanai,
Mitaro Namiki,
Masaaki Kondo,
Hiroshi Nakamura:
A fine-grain dynamic sleep control scheme in MIPS R3000.
ICCD 2008: 612-617 |
2007 |
13 | EE | Kimiyoshi Usami:
Overview on Low Power SoC Design Technology.
ASP-DAC 2007: 634-636 |
2006 |
12 | EE | Naoaki Ohkubo,
Kimiyoshi Usami:
Delay modeling and static timing analysis for MTCMOS circuits.
ASP-DAC 2006: 570-575 |
11 | EE | Kimiyoshi Usami,
Naoaki Ohkubo:
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals.
ICCD 2006 |
10 | EE | Naoaki Ohkubo,
Kimiyoshi Usami:
Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits.
IEICE Transactions 89-A(12): 3482-3490 (2006) |
2002 |
9 | EE | Kimiyoshi Usami,
Naoyuki Kawabe,
Masayuki Koizumi,
Katsuhiro Seta,
Toshiyuki Furusawa:
Automated selective multi-threshold design for ultra-low standby applications.
ISLPED 2002: 202-206 |
8 | EE | Gang Qu,
Naoyuki Kawabe,
Kimiyoshi Usami,
Miodrag Potkonjak:
Code Coverage-Based Power Estimation Techniques for Microprocessors.
Journal of Circuits, Systems, and Computers 11(5): 557- (2002) |
2000 |
7 | EE | Kimiyoshi Usami,
Mutsunori Igarashi:
Low-power design methodology and applications utilizing dual supply voltages.
ASP-DAC 2000: 123-128 |
6 | EE | Gang Qu,
Naoyuki Kawabe,
Kimiyoshi Usami,
Miodrag Potkonjak:
Function-level power estimation methodology for microprocessors.
DAC 2000: 810-813 |
1998 |
5 | | Takeshi Kitahara,
Fumihiro Minami,
Toshiaki Ueda,
Kimiyoshi Usami,
Seiichi Nishio,
Masami Murakata,
Takashi Mitsuhashi:
A Clock-Gating Method for Low-Power LSI Design.
ASP-DAC 1998: 307-312 |
4 | EE | Kimiyoshi Usami,
Mutsunori Igarashi,
Takashi Ishikawa,
Masahiro Kanazawa,
Masafumi Takahashi,
Mototsugu Hamada,
Hideho Arakida,
Toshihiro Terazawa,
Tadahiro Kuroda:
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.
DAC 1998: 483-488 |
1997 |
3 | EE | Mutsunori Igarashi,
Kimiyoshi Usami,
Kazutaka Nogami,
Fumihiro Minami,
Yukio Kawasaki,
Takahiro Aoki,
Midori Takano,
Chiharo Mizuno,
Takashi Ishikawa,
Masahiro Kanazawa,
Shinji Sonoda,
Makoto Ichida,
Naoyuki Hatanaka:
A low-power design method using multiple supply voltages.
ISLPED 1997: 36-41 |
1995 |
2 | EE | Kimiyoshi Usami,
Mark Horowitz:
Clustered voltage scaling technique for low-power design.
ISLPD 1995: 3-8 |
1990 |
1 | EE | Nobu Matsumoto,
Yoko Watanabe,
Kimiyoshi Usami,
Yukio Sugeno,
Hiroshi Hatada,
Shojiro Mori:
Datapath Generator Based on Gate-Level Symbolic Layout.
DAC 1990: 388-393 |