44. DAC 2007:
San Diego,
CA,
USA
Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007.
IEEE 2007 BibTeX
Keynotes
Trusted Hardware
Panel
Industrial Application of System Level Methods
- Walter H. Tibboel, Víctor Reyes, Martin Klompstra, Dennis Alders:
System-Level Design Flow Based on a Functional Reference for HW and SW.
23-28
Electronic Edition (link) BibTeX
- Hiren D. Patel, Sandeep K. Shukla:
Model-driven Validation of SystemC Designs.
29-34
Electronic Edition (link) BibTeX
- Bishnupriya Bhattacharya, John Rose, Stuart Swan:
Language Extensions to SystemC: Process Control Constructs.
35-38
Electronic Edition (link) BibTeX
- Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya:
Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.
39-42
Electronic Edition (link) BibTeX
Novel Techniques for Interconnect
Formal and Semi-Formal Verification Techniques
Leakage Power Analysis and Optimization
- De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang:
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization.
81-86
Electronic Edition (link) BibTeX
- Jie Gu, Sachin S. Sapatnekar, Chris H. Kim:
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift.
87-92
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- Khaled R. Heloue, Navid Azizi, Farid N. Najm:
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation.
93-98
Electronic Edition (link) BibTeX
- Tao Li, Zhiping Yu:
Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage.
99-102
Electronic Edition (link) BibTeX
- Jun Seomun, Jaehyun Kim, Youngsoo Shin:
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits.
103-106
Electronic Edition (link) BibTeX
Panel
Energy and Performance Issues in On-Chip Communication Networks
Circuit Simulation
- Shweta Srivastava, Jaijeet S. Roychowdhury:
Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations.
136-141
Electronic Edition (link) BibTeX
- Zhichun Wang, Xiaolue Lai, Jaijeet S. Roychowdhury:
PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels.
142-147
Electronic Edition (link) BibTeX
- Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan:
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.
148-153
Electronic Edition (link) BibTeX
- Suwen Yang, Mark R. Greenstreet:
Simulating Improbable Events.
154-157
Electronic Edition (link) BibTeX
- Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy:
SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits.
158-161
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Signal and Power Delivery Integrity
- Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan:
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.
162-167
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- Behnam Amelifard, Massoud Pedram:
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network.
168-173
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- Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer:
Top-k Aggressors Sets in Delay Noise Analysis.
174-179
Electronic Edition (link) BibTeX
- Zhanyuan Jiang, Shiyan Hu, Weiping Shi:
A New Twisted Differential Line Structure in Global Bus Design.
180-183
Electronic Edition (link) BibTeX
- Abinash Roy, Noha Mahmoud, Masud H. Chowdhury:
Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew.
184-187
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Functional Verification of ESL Models
Panel
Memories in Embedded Systems
- Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo:
Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design.
212-217
Electronic Edition (link) BibTeX
- Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani B. Srivastava:
A System For Coarse Grained Memory Protection In Tiny Embedded Processors.
218-223
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- Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli, Ozcan Ozturk:
Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors.
224-229
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- Liping Xue, Ozcan Ozturk, Mahmut T. Kandemir:
A Memory-Conscious Code Parallelization Scheme.
230-233
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- Ann Gordon-Ross, Frank Vahid:
A Self-Tuning Configurable Cache.
234-237
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Statistical Techniques for Timing Analysis and Design
- Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James Tschanz, Vivek De:
Comparative Analysis of Conventional and Statistical Design Techniques.
238-243
Electronic Edition (link) BibTeX
- Zhuo Feng, Peng Li, Yaping Zhan:
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction.
244-249
Electronic Edition (link) BibTeX
- Lerong Cheng, Jinjun Xiong, Lei He:
Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources.
250-255
Electronic Edition (link) BibTeX
- Amith Singhee, Rob A. Rutenbar:
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting.
256-261
Electronic Edition (link) BibTeX
Wild and Crazy Ideas (WACI)
- Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz:
Chip Multi-Processor Generator.
262-263
Electronic Edition (link) BibTeX
- Stephen A. Edwards, Edward A. Lee:
The Case for the Precision Timed (PRET) Machine.
264-265
Electronic Edition (link) BibTeX
- Paul Bogdan, Radu Marculescu:
Quantum-Like Effects in Network-on-Chip Buffers Behavior.
266-267
Electronic Edition (link) BibTeX
- Farinaz Koushanfar, Miodrag Potkonjak:
CAD-based Security, Cryptography, and Digital Rights Management.
268-269
Electronic Edition (link) BibTeX
- Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester:
Line-End Shortening is Not Always a Failure.
270-271
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- Steven P. Levitan:
You Can Get There From Here: Connectivity of Random Graphs on Grids.
272-273
Electronic Edition (link) BibTeX
- Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy:
High Performance and Low Power Electronics on Flexible Substrate.
274-275
Electronic Edition (link) BibTeX
- J. Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot:
Novel CNTFET-based Reconfigurable Logic Gate Design.
276-277
Electronic Edition (link) BibTeX
Distributed Computing:
Automotive Network Design and Analysis
- Abhijit Davare, Qi Zhu, Marco Di Natale, Claudio Pinello, Sri Kanajan, Alberto L. Sangiovanni-Vincentelli:
Period Optimization for Hard Real-time Distributed Automotive Systems.
278-283
Electronic Edition (link) BibTeX
- Andrei Hagiescu, Unmesh D. Bordoloi, Samarjit Chakraborty, Prahladavaradan Sampath, P. Vignesh V. Ganesan, Sethu Ramesh:
Performance Analysis of FlexRay-based ECU Networks.
284-289
Electronic Edition (link) BibTeX
- Juan R. Pimentel, Jason Paskvan:
Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application.
290-293
Electronic Edition (link) BibTeX
- Zonghua Gu, Xiuqiang He, Mingxuan Yuan:
Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking.
294-299
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Emerging Nanoscale Hybrid Circuits and Architectures
Physical Implementation of FPGAs
Process Aware Physical Design
Reliable Design and CAD Solutions for Circuit Aging
- Kunhyuk Kang, Kee-Jong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy:
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.
358-363
Electronic Edition (link) BibTeX
- Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao:
The Impact of NBTI on the Performance of Combinational and Sequential Circuits.
364-369
Electronic Edition (link) BibTeX
- Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
NBTI-Aware Synthesis of Digital Circuits.
370-375
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Silicon,
Safety and Self-Driving Cars
Silicon Measurement Correlation to Reliability,
Noise and Timing Effects
Optimizing Arithmetic and Communication
Analog and RF Simulation
- Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram:
Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency.
424-429
Electronic Edition (link) BibTeX
- Henry H. Y. Chan, Zeljko Zilic:
Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops.
430-435
Electronic Edition (link) BibTeX
- Wei Dong, Peng Li:
Accelerating Harmonic Balance Simulation Using Efficient Parallelizable Hierarchical Preconditioning.
436-439
Electronic Edition (link) BibTeX
- Jaeha Kim, Kevin D. Jones, Mark A. Horowitz:
Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch.
440-443
Electronic Edition (link) BibTeX
Panel
Panel
Modern Placement Techniques
- Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu:
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.
447-452
Electronic Edition (link) BibTeX
- Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu:
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
453-458
Electronic Edition (link) BibTeX
- Huaizhi Wu, Martin D. F. Wong:
Improving Voltage Assignment by Outlier Detection and Incremental Placement.
459-464
Electronic Edition (link) BibTeX
- Po-Hung Lin, Shyh-Chang Lin:
Analog Placement Based on Novel Symmetry-Island Formulation.
465-470
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Advances in Embedded Hardware Design
Bridging the Gap with Silicon
Practical Solutions for Power-Aware Testing
- Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra:
Scan Test Planning for Power Reduction.
521-526
Electronic Edition (link) BibTeX
- Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja:
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.
527-532
Electronic Edition (link) BibTeX
- Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram:
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design.
533-538
Electronic Edition (link) BibTeX
- Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer:
New Test Data Decompressor for Low Power Applications.
539-544
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Virtual Automotive Platforms
The Future of Interconnects:
How Will Billions of Transistors Communicate in the Nanometer Era
- Kerry Bernstein, Paul Andry, Jerome Cann, Philip G. Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steve Koester, John Magerlein, Ruchir Puri, Albert M. Young:
Interconnects in the Third Dimension: Design Challenges for 3D ICs.
562-567
Electronic Edition (link) BibTeX
- Azad Naeemi, Reza Sarvari, James D. Meindl:
Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects.
568-573
Electronic Edition (link) BibTeX
- Jaijeet S. Roychowdhury:
Micro-Photonic Interconnects: Characteristics, Possibilities and Limitations.
574-575
Electronic Edition (link) BibTeX
- Louis Scheffer:
CAD Implications of New Interconnect Technologies.
576-581
Electronic Edition (link) BibTeX
Advances in Decision Procedures
3D IC and Package Design Issues
- Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang:
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design.
606-611
Electronic Edition (link) BibTeX
- Krishna Bharath, Ege Engin, Madhavan Swaminathan, Kazuhide Uriu, Toru Yamada:
Computationally Efficient Power Integrity Simulation for System-on-Package Applications.
612-617
Electronic Edition (link) BibTeX
- Hao Yu, Chunta Chu, Lei He:
Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design.
618-621
Electronic Edition (link) BibTeX
- Kiran Puttaswamy, Gabriel H. Loh:
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors.
622-625
Electronic Edition (link) BibTeX
- Brent Goplen, Sachin S. Sapatnekar:
Placement of 3D ICs with Thermal and Interlayer Via Considerations.
626-631
Electronic Edition (link) BibTeX
Panel
Synthetic Biology:
An Emerging Discipline with New Engineering Rules and Design Tools
Programming and Scheduling Embedded Systems
Emerging Test Solutions
Circuit Level Power Analysis and Low Power Design
- Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw:
Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design.
694-699
Electronic Edition (link) BibTeX
- Scott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw:
Nanometer Device Scaling in Subthreshold Circuits.
700-705
Electronic Edition (link) BibTeX
- Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke:
Efficient Modeling Techniques for Dynamic Voltage Drop Analysis.
706-711
Electronic Edition (link) BibTeX
- Ashesh Rastogi, Wei Chen, Sandip Kundu:
On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method.
712-715
Electronic Edition (link) BibTeX
- Yongsoo Joo, Youngjin Cho, Donghwa Shin, Naehyuck Chang:
Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash Memory.
716-719
Electronic Edition (link) BibTeX
Parameter Tuning in System Architecture Exploration
- Alex Bobrek, JoAnn M. Paul, Donald E. Thomas:
Shared Resource Access Attributes for High-Level Contention Models.
720-725
Electronic Edition (link) BibTeX
- Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha:
A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices.
726-731
Electronic Edition (link) BibTeX
- Peter Hallschmid, Resve Saleh:
Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling.
732-737
Electronic Edition (link) BibTeX
- Balaji Raman, Samarjit Chakraborty, Wei Tsang Ooi, Santanu Dutta:
Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution.
738-743
Electronic Edition (link) BibTeX
Panel
Thousand-Core Chips
- Shekhar Borkar:
Thousand Core ChipsA Technology Perspective.
746-749
Electronic Edition (link) BibTeX
- Anant Agarwal, Markus Levy:
The KILL Rule for Multicore.
750-753
Electronic Edition (link) BibTeX
- Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel:
Implicitly Parallel Programming Models for Thousand-Core Microprocessors.
754-759
Electronic Edition (link) BibTeX
- John A. Darringer:
Multi-Core Design Automation Challenges.
760-764
Electronic Edition (link) BibTeX
Communication-Based Resource Allocation
- Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim:
Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture.
765-770
Electronic Edition (link) BibTeX
- Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera:
Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.
771-776
Electronic Edition (link) BibTeX
- Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal:
Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs.
777-782
Electronic Edition (link) BibTeX
- Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea, Seth Copen Goldstein:
Global Critical Path: A Tool for System-Level Timing Analysis.
783-786
Electronic Edition (link) BibTeX
- Pramod Chandraiah, Rainer Dömer:
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification.
787-790
Electronic Edition (link) BibTeX
Embedded Processor and MPSoC Design
Modeling Technology Impact
- Frank Liu:
A General Framework for Spatial Correlation Modeling in VLSI Design.
817-822
Electronic Edition (link) BibTeX
- Ritu Singhal, Asha Balijepalli, Anupama Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao:
Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.
823-828
Electronic Edition (link) BibTeX
- Guo Yu, Wei Dong, Zhuo Feng, Peng Li:
A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis.
829-834
Electronic Edition (link) BibTeX
- Ying Zhou, Zhuo Li, Weiping Shi:
Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method.
835-840
Electronic Edition (link) BibTeX
Technology Mapping and Physical Synthesis
System-Level Power Management and Analysis
- Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan:
SODA: Sensitivity Based Optimization of Disk Architecture.
865-870
Electronic Edition (link) BibTeX
- Jianli Zhuo, Chaitali Chakrabarti, Kyungsoo Lee, Naehyuck Chang:
Dynamic Power Management with Hybrid Power Sources.
871-876
Electronic Edition (link) BibTeX
- Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
System-on-Chip Power Management Considering Leakage Power Variations.
877-882
Electronic Edition (link) BibTeX
- Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan:
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.
883-886
Electronic Edition (link) BibTeX
- Hung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang:
A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages.
887-890
Electronic Edition (link) BibTeX
Dynamic Verification of Processors and Processor-Based Designs
- Shady Copty, Itai Jaeger, Yoav Katz, Michael Vinov:
Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation.
891-895
Electronic Edition (link) BibTeX
- Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang:
Automatic Verification of External Interrupt Behaviors for Microprocessor Design.
896-901
Electronic Edition (link) BibTeX
- Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jaeger, Ofer Peled:
A Framework for the Validation of Processor Architecture Compliance.
902-905
Electronic Edition (link) BibTeX
- Oleg Petlin, Wilson Snyder:
Functional Verification of SiCortex Multiprocessor System-on-a-Chip.
906-909
Electronic Edition (link) BibTeX
FPGA Tools and Methodologies
Mixed-Signal Modeling,
Methodology and Synthesis
Design Methods and Manufacturability Solutions for Emerging Technologies
- Tao Xu, Krishnendu Chakrabarty:
Integrated Droplet Routing in the Synthesis of Microfluidic Biochips.
948-953
Electronic Edition (link) BibTeX
- Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska:
OPC-Free and Minimally Irregular IC Design Style.
954-957
Electronic Edition (link) BibTeX
- Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra:
Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.
958-961
Electronic Edition (link) BibTeX
- Dmitri Maslov, Sean M. Falconer, Michele Mosca:
Quantum Circuit Placement: Optimizing Qubit-to-qubit Interactions through Mapping Quantum Circuits into a Physical Experiment.
962-965
Electronic Edition (link) BibTeX
- Tsung-Ching Huang, Huai-Yuan Tseng, Chen-Pang Kung, Kwang-Ting Cheng:
Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si: H TFT Scan Driver.
966-969
Electronic Edition (link) BibTeX
High-Performance Synchronization Techniques
- Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh:
Clock Period Minimization with Minimum Delay Insertion.
970-975
Electronic Edition (link) BibTeX
- Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs.
976-981
Electronic Edition (link) BibTeX
- Nikolaos Andrikos, Luciano Lavagno, Davide Pandini, Christos P. Sotiriou:
A Fully-Automated Desynchronization Flow for Synchronous Circuits.
982-985
Electronic Edition (link) BibTeX
- Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein:
Self-Resetting Latches for Asynchronous Micro-Pipelines.
986-989
Electronic Edition (link) BibTeX
Panel
Copyright © Sat May 16 23:04:39 2009
by Michael Ley (ley@uni-trier.de)
