José Monteiro
List of publications from the DBLP Bibliography Server - FAQ
2009 | ||
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37 | EE | Lars Svensson, José Monteiro: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers Springer 2009 |
36 | EE | António Gusmão, L. Miguel Silveira, José C. Monteiro: Parameter tuning in SVM-based power macro-modeling. ISQED 2009: 135-140 |
2008 | ||
35 | EE | Pedro Marques Morgado, Paulo F. Flores, José C. Monteiro, Luis Miguel Silveira: Generating Worst-Case Stimuli for Accurate Power Grid Analysis. PATMOS 2008: 247-257 |
34 | EE | Levent Aksoy, Eduardo da Costa, Paulo F. Flores, José Monteiro: Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1013-1026 (2008) |
2007 | ||
33 | EE | Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José C. Monteiro: Optimization of Area in Digital FIR Filters using Gate-Level Metrics. DAC 2007: 420-423 |
32 | EE | Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi: A new array architecture for signed multiplication using Gray encoded radix-2m operands. Integration 40(2): 118-132 (2007) |
2006 | ||
31 | EE | Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro: Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. DAC 2006: 669-674 |
30 | EE | Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro: Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. SBCCI 2006: 161-166 |
2005 | ||
29 | Paulo F. Flores, José C. Monteiro, Eduardo A. C. da Costa: An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. ICCAD 2005: 13-16 | |
28 | EE | M. Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro: Design of a radix-2m hybrid array multiplier using carry save adder format. SBCCI 2005: 172-177 |
27 | EE | Leonardo L. de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José C. Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis: A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. VLSI-SoC 2005: 25-39 |
2004 | ||
26 | EE | Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi: An improved synthesis method for low power hardwired FIR filters. SBCCI 2004: 237-241 |
2003 | ||
25 | EE | Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro: A New Pipelined Array Architecture for Signed Multiplication. SBCCI 2003: 65-70 |
24 | Eduardo A. C. da Costa, José Monteiro, Sergio Bampi: Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. VLSI-SOC 2003: 307- | |
2002 | ||
23 | EE | Eduardo A. C. da Costa, Sergio Bampi, José Monteiro: A New Architecture for Signed Radix-2m Pure Array Multipliers. ICCD 2002: 112-117 |
22 | EE | José C. Monteiro, Arlindo L. Oliveira: Implicit FSM decomposition applied to low-power design. IEEE Trans. VLSI Syst. 10(5): 560-565 (2002) |
2000 | ||
21 | EE | José C. Monteiro, Arlindo L. Oliveira: FSM decomposition by direct circuit manipulation applied to low power design. ASP-DAC 2000: 351-358 |
20 | José C. Costa, Srinivas Devadas, José Monteiro: Observability Analysis of Embedded Software for Coverage-Directed Validation. ICCAD 2000: 27-32 | |
19 | EE | Ricardo Ferreira, A.-M. Trullemans, José C. Costa, José Monteiro: Probabilistic Bottom-Up RTL Power Estimation. ISQED 2000: 439- |
1999 | ||
18 | Antônio Mota, Nuno Ferreira, Arlindo L. Oliveira, José C. Monteiro: Integrating Dynamic Power Management in the Design Flow. VLSI 1999: 233-244 | |
17 | EE | Paulo F. Flores, José C. Costa, Horácio C. Neto, José C. Monteiro, João P. Marques Silva: Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. VLSI Design 1999: 37-41 |
16 | Srinivas Devadas, Sharad Malik, José C. Monteiro, Luciano Lavagno: CAD Techniques for Embedded System Design. VLSI Design 1999: 608 | |
1998 | ||
15 | EE | José C. Monteiro, Arlindo L. Oliveira: Finite State Machine Decomposition For Low Power. DAC 1998: 758-763 |
14 | EE | José C. Monteiro, Srinivas Devadas, Abhijit Ghosh: Sequential logic optimization for low power using input-disabling precomputation architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 279-284 (1998) |
1997 | ||
13 | EE | José C. Costa, José C. Monteiro, Srinivas Devadas: Switching activity estimation using limited depth reconvergent path analysis. ISLPED 1997: 184-189 |
12 | EE | José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White: Estimation of average switching activity in combinational logic circuits using symbolic simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 121-127 (1997) |
1996 | ||
11 | EE | José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar: Scheduling Techniques to Enable Power Management. DAC 1996: 349-352 |
10 | EE | Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin: Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. IEEE Trans. VLSI Syst. 4(4): 495 (1996) |
9 | EE | José Monteiro, Srinivas Devadas: Techniques for power estimation and optimization at the logic level: A survey. VLSI Signal Processing 13(2-3): 259-276 (1996) |
1995 | ||
8 | EE | José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh: Optimization of combinational and sequential logic circuits for low power using precomputation. ARVLSI 1995: 430-444 |
7 | EE | José Monteiro, Srinivas Devadas: Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. ISLPD 1995: 33-38 |
6 | EE | Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin: Power estimation methods for sequential logic circuits. IEEE Trans. VLSI Syst. 3(3): 404-416 (1995) |
1994 | ||
5 | EE | José C. Monteiro, Srinivas Devadas, Bill Lin: A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. DAC 1994: 12-17 |
4 | EE | Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. ICCAD 1994: 74-81 |
3 | José C. Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto: Bitwise Encoding of Finite State Machines. VLSI Design 1994: 379-382 | |
2 | EE | Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. IEEE Trans. VLSI Syst. 2(4): 426-436 (1994) |
1993 | ||
1 | EE | José C. Monteiro, Srinivas Devadas, Abhijit Ghosh: Retiming sequential circuits for low power. ICCAD 1993: 398-402 |