Jens Leenstra

2008
11	EE	Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding: Scan chain clustering for test power reduction. DAC 2008: 828-833
2007
10	EE	Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra: Scan Test Planning for Power Reduction. DAC 2007: 521-526
9	EE	Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata: Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM Journal of Research and Development 51(5): 529-544 (2007)
8	EE	Lee Eisen, John Wesley Ward III, Hans-Werner Tast, Nicolas Mäding, Jens Leenstra, Silvia M. Müller, Christian Jacobi, Jochen Preiss, Eric M. Schwarz, Steven R. Carlough: IBM POWER6 accelerators: VMX and DFU. IBM Journal of Research and Development 51(6): 663-684 (2007)
7	EE	Joachim Fenkes, Tobias Gemmeke, Jens Leenstra: Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process. J. Low Power Electronics 3(1): 54-59 (2007)
2006
6	EE	Nicolas Mäding, Jens Leenstra, Juergen Pille, R. Sautter, S. Büttner, S. Ehrenreich, W. Haller: The vector fixed point unit of the synergistic processor element of the cell architecture processor. DATE Designers' Forum 2006: 244-248
2001
5		Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich: Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. ITC 2001: 461-469
2000
4	EE	David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel: Custom circuit design as a driver of microprocessor performance. IBM Journal of Research and Development 44(6): 799-822 (2000)
1997
3	EE	Jörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile: Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors. DAC 1997: 89-94
1991
2		Jens Leenstra, Lambert Spaanenburg: Hierarchical Test Program Development for Scan Testable Circuits. ITC 1991: 375-384
1989
1		Jens Leenstra, Lambert Spaanenburg: On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems. ITC 1989: 838-845

Coauthor Index

1	David H. Allen	[4]
2	Shigehiro Asano	[9]
3	Daniel A. Brokenshire	[9]
4	S. Büttner	[6]
5	Steven R. Carlough	[8]
6	Sang H. Dhong	[4] [9]
7	Gerhard Döttling	[3]
8	S. Ehrenreich	[6]
9	Lee Eisen	[8]
10	Melanie Elm	[11]
11	Joachim Fenkes	[7]
12	Brian K. Flachs	[9]
13	Tobias Gemmeke	[7]
14	Gilles Gervais	[9]
15	W. Haller	[6]
16	Akiyuki Hatakeyama	[9]
17	Koji Hirairi	[9]
18	H. Peter Hofstee	[4] [9]
19	Michael E. Imhof	[10] [11]
20	Eiji Iwata	[9]
21	Christian Jacobi	[8]
22	Kevin W. Kark	[3]
23	Atsushi Kawasumi	[9]
24	Michael Kessler	[5]
25	Gundolf Kiefer	[5]
26	Roy Kim	[9]
27	Tien Le	[9]
28	Bernd Leppla	[3]
29	John S. Liberty	[9]
30	Peichun Liu	[9]
31	Nicolas Mäding	[6] [8] [10] [11]
32	Brad W. Michael	[9]
33	Silvia M. Müller	[8] [9]
34	Hans-Jürgen Münster	[3]
35	Hiroaki Murakami	[9]
36	Hiromi Noro	[9]
37	Kevin J. Nowka	[4]
38	Hwa-Joon Oh	[9]
39	Shoji Onishi	[9]
40	Mohammad Peyravian	[9]
41	Juergen Pille	[6] [9]
42	Jochen Preiss	[8]
43	R. Sautter	[6]
44	Knut Schünemann	[5]
45	Eric M. Schwarz	[8]
46	Thomas Schwarz	[5]
47	Joel Silberman	[9]
48	Lambert Spaanenburg	[1] [2]
49	Daniel L. Stasiak	[4]
50	Osamu Takahashi	[9]
51	Hans-Werner Tast	[8]
52	VanDung To	[9]
53	Jörg A. Walter	[3]
54	John Wesley Ward III	[8]
55	Yukio Watanabe	[9]
56	Dieter F. Wendel	[4]
57	Bruce Wile	[3]
58	Hans-Joachim Wunderlich	[5] [10] [11]
59	Naoka Yano	[9]
60	Suksoon Yong	[9]
61	Christian G. Zoellin	[10] [11]

Colors in the list of coauthors