| 2007 |
|---|
| 4 | EE | Henry H. Y. Chan,
Zeljko Zilic:
Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops.
DAC 2007: 430-435 |
| 3 | EE | Henry H. Y. Chan,
Zeljko Zilic:
A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits.
ISCAS 2007: 2934-2937 |
| 2005 |
|---|
| 2 | EE | Henry H. Y. Chan,
Zeljko Zilic:
Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization.
ISQED 2005: 390-395 |
| 2004 |
|---|
| 1 | EE | Henry H. Y. Chan,
Zeljko Zilic:
Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach.
ISQED 2004: 309-314 |
