dblp.uni-trier.dewww.uni-trier.de

Henry H. Y. Chan

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2007
4EEHenry H. Y. Chan, Zeljko Zilic: Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. DAC 2007: 430-435
3EEHenry H. Y. Chan, Zeljko Zilic: A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. ISCAS 2007: 2934-2937
2005
2EEHenry H. Y. Chan, Zeljko Zilic: Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization. ISQED 2005: 390-395
2004
1EEHenry H. Y. Chan, Zeljko Zilic: Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach. ISQED 2004: 309-314

Coauthor Index

1Zeljko Zilic [1] [2] [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)