| 2007 |
|---|
| 5 | EE | Steven M. Burns,
Mahesh Ketkar,
Noel Menezes,
Keith A. Bowman,
James Tschanz,
Vivek De:
Comparative Analysis of Conventional and Statistical Design Techniques.
DAC 2007: 238-243 |
| 4 | EE | Shiyan Hu,
Mahesh Ketkar,
Jiang Hu:
Gate Sizing For Cell Library-Based Designs.
DAC 2007: 847-852 |
| 2002 |
|---|
| 3 | EE | Mahesh Ketkar,
Sachin S. Sapatnekar:
Standby power optimization via transistor sizing and dual threshold voltage assignment.
ICCAD 2002: 375-378 |
| 2000 |
|---|
| 2 | EE | Mahesh Ketkar,
Kishore Kasamsetty,
Sachin S. Sapatnekar:
Convex delay models for transistor sizing.
DAC 2000: 655-660 |
| 1 | EE | Kishore Kasamsetty,
Mahesh Ketkar,
Sachin S. Sapatnekar:
A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates].
IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 779-788 (2000) |
