2008 |
16 | EE | Ruchir Puri,
Devadas Varma,
Darvin Edwards,
Alan J. Weger,
Paul Franzon,
Andrew Yang,
Stephen V. Kosonocky:
Keeping hot chips cool: are IC thermal problems hot air?
DAC 2008: 634-635 |
2007 |
15 | EE | Matthew M. Ziegler,
Gary S. Ditlow,
Stephen V. Kosonocky,
Zhenyu Qi,
Mircea R. Stan:
Structured and tuned array generation (STAG) for high-performance random logic.
ACM Great Lakes Symposium on VLSI 2007: 257-262 |
14 | EE | Gila Kamhi,
Sarah Miller,
Stephen Bailey Mentor,
Wolfgang Nebel,
Y. C. Wong,
Juergen Karmann,
Enrico Macii,
Stephen V. Kosonocky,
Steve Curtis:
Early Power-Aware Design & Validation: Myth or Reality?
DAC 2007: 210-211 |
13 | EE | Zhenyu Qi,
Matthew M. Ziegler,
Stephen V. Kosonocky,
Jan M. Rabaey,
Mircea R. Stan:
Multi-Dimensional Circuit and Micro-Architecture Level Optimization.
ISQED 2007: 275-280 |
2005 |
12 | EE | Phillip Chin,
Charles A. Zukowski,
George Gristede,
Stephen V. Kosonocky:
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies.
Integration 38(3): 491-504 (2005) |
2004 |
11 | EE | Phillip Chin,
Charles A. Zukowski,
George Gristede,
Stephen V. Kosonocky:
Characterization of logic circuit techniques for high leakage CMOS technologies.
ACM Great Lakes Symposium on VLSI 2004: 230-235 |
10 | EE | Suhwan Kim,
Stephen V. Kosonocky,
Daniel R. Knebel,
Kevin G. Stawiasz:
Experimental measurement of a novel power gating structure with intermediate power saving mode.
ISLPED 2004: 20-25 |
2003 |
9 | EE | Suhwan Kim,
Stephen V. Kosonocky,
Daniel R. Knebel:
Understanding and minimizing ground bounce during mode transition of power gating structures.
ISLPED 2003: 22-25 |
8 | EE | Stephen V. Kosonocky,
Azeez J. Bhavnagarwala,
Kenneth Chin,
George Gristede,
Anne-Marie Haen,
Wei Hwang,
Mark B. Ketchen,
Suhwan Kim,
Daniel R. Knebel,
Kevin W. Warren,
Victor V. Zyuban:
Low-power circuits and technology for wireless digital systems.
IBM Journal of Research and Development 47(2-3): 283-298 (2003) |
7 | EE | Jean-Olivier Plouchart,
Noah Zamdmer,
Jonghae Kim,
Melanie Sherony,
Yue Tan,
Asit Ray,
Mohamed Talbi,
Lawrence F. Wagner,
Kun Wu,
Naftali E. Lustig,
Shreesh Narasimha,
Patricia O'Neil,
Nghia Phan,
Michael Rohn,
James Strom,
David M. Friend,
Stephen V. Kosonocky,
Daniel R. Knebel,
Suhwan Kim,
Keith A. Jenkins,
Michel M. Rivier:
Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits.
IBM Journal of Research and Development 47(5-6): 611-630 (2003) |
2002 |
6 | EE | Victor V. Zyuban,
Stephen V. Kosonocky:
Low power integrated scan-retention mechanism.
ISLPED 2002: 98-102 |
5 | EE | Alice Wang,
Anantha Chandrakasan,
Stephen V. Kosonocky:
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits.
ISVLSI 2002: 7-14 |
2001 |
4 | | Azeez J. Bhavnagarwala,
Stephen V. Kosonocky,
James D. Meindl:
Interconnect-centric Array Architectures for Minimum SRAM Access Time.
ICCD 2001: 400-405 |
3 | EE | Stephen V. Kosonocky,
Michael Immediato,
Peter E. Cottrell,
Terence B. Hook,
Randy W. Mann,
Jeff Brown:
Enchanced multi-threshold (MTCMOS) circuits using variable well bias.
ISLPED 2001: 165-169 |
2 | EE | W. Chen,
Wei Hwang,
Prabhakar Kudva,
George Gristede,
Stephen V. Kosonocky,
Rajiv V. Joshi:
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.
ISLPED 2001: 263-266 |
1998 |
1 | EE | Stephen V. Kosonocky,
Arthur A. Bright,
Kevin W. Warren,
Ruud A. Haring,
Steve Klepner,
Sameh W. Asaad,
S. Basavaiah,
Bob Havreluk,
David F. Heidel,
Michael Immediato,
Keith A. Jenkins,
Rajiv V. Joshi,
Ben Parker,
T. V. Rajeevakumar,
Kevin G. Stawiasz:
Designing a Testable System on a Chip.
VTS 1998: 2-7 |