| 2008 |
|---|
| 42 | EE | Krishnan Sundaresan,
Nihar R. Mahapatra:
Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses.
ISQED 2008: 118-122 |
| 41 | EE | Srivathsan Krishnamohan,
Nihar R. Mahapatra:
Slack redistribution in pipelined circuits for enhanced soft-error rate reduction.
SoCC 2008: 159-162 |
| 40 | EE | Kaushal R. Gandhi,
Nihar R. Mahapatra:
Partitioned reuse cache for energy-efficient soft-error protection of functional units.
SoCC 2008: 17-20 |
| 39 | EE | Jiangjiang Liu,
Nihar R. Mahapatra:
The role of interconnects in the performance scalability of multicore architectures.
SoCC 2008: 21-24 |
| 38 | EE | Sharath Jayaprakash,
Nihar R. Mahapatra:
Energy-optimal signaling and ordering of bits for area-constrained interconnects.
SoCC 2008: 9-12 |
| 37 | EE | Kaushal R. Gandhi,
Nihar R. Mahapatra:
Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass.
VLSI Design 2008: 45-51 |
| 2007 |
|---|
| 36 | EE | Krishnan Sundaresan,
Nihar R. Mahapatra:
An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires.
DAC 2007: 515-520 |
| 35 | EE | Sharath Jayaprakash,
Nihar R. Mahapatra:
Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses.
VLSI Design 2007: 127-134 |
| 34 | EE | Nihar R. Mahapatra,
Shantanu Dutt:
An efficient delay-optimal distributed termination detection algorithm.
J. Parallel Distrib. Comput. 67(10): 1047-1066 (2007) |
| 2006 |
|---|
| 33 | EE | Jiangjiang Liu,
Krishnan Sundaresan,
Nihar R. Mahapatra:
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction.
ACM Great Lakes Symposium on VLSI 2006: 111-114 |
| 32 | EE | Kaushal R. Gandhi,
Nihar R. Mahapatra:
Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits.
DATE 2006: 1001-1006 |
| 31 | EE | Krishnan Sundaresan,
Nihar R. Mahapatra:
Value-based bit ordering for energy optimization of on-chip global signal buses.
DATE 2006: 624-625 |
| 30 | EE | Jiangjiang Liu,
Krishnan Sundaresan,
Nihar R. Mahapatra:
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses.
ICCD 2006 |
| 2005 |
|---|
| 29 | EE | Srivathsan Krishnamohan,
Nihar R. Mahapatra:
Analysis and design of soft-error hardened latches.
ACM Great Lakes Symposium on VLSI 2005: 328-331 |
| 28 | EE | Srivathsan Krishnamohan,
Nihar R. Mahapatra:
An analysis of the robustness of CMOS delay elements.
ACM Great Lakes Symposium on VLSI 2005: 412-415 |
| 27 | EE | Srivathsan Krishnamohan,
Nihar R. Mahapatra:
Increasing the energy efficiency of pipelined circuits via slack redistribution.
ACM Great Lakes Symposium on VLSI 2005: 436-441 |
| 26 | EE | Srivathsan Krishnamohan,
Nihar R. Mahapatra:
Combining Error Masking and Error Detection Plus Recovery to Combat Soft Errors in Static CMOS Circuits.
DSN 2005: 40-49 |
| 25 | EE | Krishnan Sundaresan,
Nihar R. Mahapatra:
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses.
HPCA 2005: 51-60 |
| 24 | EE | Kaushal R. Gandhi,
Nihar R. Mahapatra:
Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units.
VLSI Design 2005: 570-575 |
| 23 | EE | Jiangjiang Liu,
Krishnan Sundaresan,
Nihar R. Mahapatra:
Energy-Efficient Compressed Address Transmission.
VLSI Design 2005: 592-597 |
| 22 | EE | Krishnan Sundaresan,
Nihar R. Mahapatra:
An Accurate Energy and Thermal Model for Global Signal Buses.
VLSI Design 2005: 685-690 |
| 2004 |
|---|
| 21 | EE | Srivathsan Krishnamohan,
Nihar R. Mahapatra:
A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits.
ICCD 2004: 126-131 |
| 20 | EE | Jiangjiang Liu,
Krishnan Sundaresan,
Nihar R. Mahapatra:
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study.
ICCD 2004: 458-463 |
| 19 | EE | Nihar R. Mahapatra,
Shantanu Dutt:
Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems.
Parallel Computing 30(5-6): 867-881 (2004) |
| 2003 |
|---|
| 18 | EE | Nihar R. Mahapatra,
Jiangjiang Liu,
Krishnan Sundaresan:
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis.
ICCD 2003: 234-239 |
| 17 | EE | Kaushal R. Gandhi,
Nihar R. Mahapatra:
A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units.
ICCD 2003: 426- |
| 16 | EE | Jiangjiang Liu,
Nihar R. Mahapatra,
Krishnan Sundaresan:
Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses.
ISVLSI 2003: 220-221 |
| 15 | EE | Krishnan Sundaresan,
Nihar R. Mahapatra:
Code Compression Techniques for Embedded Systems and Their Effectiveness.
ISVLSI 2003: 262-263 |
| 2002 |
|---|
| 14 | EE | Nihar R. Mahapatra,
Jiangjiang Liu,
Krishnan Sundaresan:
The performance advantage of applying compression to the memory system.
MSP/ISMM 2002: 86-96 |
| 2001 |
|---|
| 13 | EE | Nihar R. Mahapatra,
Shantanu Dutt:
Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays.
J. Parallel Distrib. Comput. 61(10): 1391-1411 (2001) |
| 2000 |
|---|
| 12 | | Nihar R. Mahapatra,
Shantanu Dutt:
Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing.
Int. J. Found. Comput. Sci. 11(2): 231-246 (2000) |
| 1999 |
|---|
| 11 | EE | Nihar R. Mahapatra,
Shantanu Dutt:
Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs.
FTCS 1999: 122-129 |
| 10 | | Nihar R. Mahapatra,
Douglas E. Covelli,
Yuval Beres:
A Quantitative Evaluation of Limited-Memory Branch-and-Bound Algorithms.
IC-AI 1999: 84-90 |
| 1998 |
|---|
| 9 | EE | Nihar R. Mahapatra,
Shantanu Dutt:
Adaptive Quality Equalizing: High-Performance Load Balancing for Parallel Branch-and-Bound Across Applications and Computing Systems.
IPPS/SPDP 1998: 796-800 |
| 1997 |
|---|
| 8 | | Shantanu Dutt,
Nihar R. Mahapatra:
Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance.
IEEE Trans. Computers 46(9): 997-1015 (1997) |
| 7 | EE | Nihar R. Mahapatra,
Shantanu Dutt:
Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search.
IEEE Trans. Parallel Distrib. Syst. 8(7): 738-756 (1997) |
| 1996 |
|---|
| 6 | | Nihar R. Mahapatra,
Shantanu Dutt:
Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers.
FTCS 1996: 272-281 |
| 5 | EE | Nihar R. Mahapatra,
Shantanu Dutt:
Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing.
IPPS 1996: 881-885 |
| 1995 |
|---|
| 4 | | Shantanu Dutt,
Nihar R. Mahapatra:
Node Covering, Error Correcting Codes and Multiprocessors with Very High Average Fault Tolerance.
FTCS 1995: 320-329 |
| 1994 |
|---|
| 3 | | Shantanu Dutt,
Nihar R. Mahapatra:
Scalable Load Balancing Strategies for Parallel A* Algorithms.
J. Parallel Distrib. Comput. 22(3): 488-505 (1994) |
| 1993 |
|---|
| 2 | | Shantanu Dutt,
Nihar R. Mahapatra:
Parallel A* Algorithms and Their Performance on Hypercube Multiprocessors.
IPPS 1993: 797-803 |
| 1 | | Nihar R. Mahapatra,
Shantanu Dutt:
Scalable Duplicate Pruning Strategies for Parallel A* Graph Search.
SPDP 1993: 290-297 |
