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Allon Adir

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2007
6EEAllon Adir, Sigal Asaf, Laurent Fournier, Itai Jaeger, Ofer Peled: A Framework for the Validation of Processor Architecture Compliance. DAC 2007: 902-905
2005
5EEAllon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, Kirill Shoikhet: A generic micro-architectural test plan approach for microprocessor verification. DAC 2005: 769-774
4EEAllon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy: VLIW: a case study of parallelism verification. DAC 2005: 779-782
2004
3EEAllon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv: Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification. IEEE Design & Test of Computers 21(2): 84-93 (2004)
2003
2EEAllon Adir, Roy Emek, Yoav Katz, Anatoly Koyfman: DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms. MTV 2003: 3-6
1EEAllon Adir, Hagit Attiya, Gil Shurek: Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture. IEEE Trans. Parallel Distrib. Syst. 14(5): 502-515 (2003)

Coauthor Index

1Eli Almog [3]
2Yaron Arbetman [4]
3Sigal Asaf [6]
4Hagit Attiya (Chagit Attiya) [1]
5Hezi Azatchi [5]
6Eyal Bin [5]
7Massimo A. Calligaro [4]
8Andrew Cofler [4]
9Bella Dubrov [4]
10Gabriel Duffy [4]
11Roy Emek [2]
12Laurent Fournier [3] [6]
13Itai Jaeger [6]
14Yoav Katz [2]
15Anatoly Koyfman [2]
16Yossi Lichtenstein [4]
17Eitan Marcus [3]
18Ofer Peled [5] [6]
19Michal Rimon [3] [4]
20Kirill Shoikhet [5]
21Gil Shurek [1]
22Michael Vinov [3] [4]
23Avi Ziv [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)