Anmol Mathur

2009
17	EE	Anmol Mathur, Qi Wang: Power Reduction Techniques and Flows at RTL and System Level. VLSI Design 2009: 28-29
2007
16	EE	Anmol Mathur, Venkat Krishnaswamy: Design for Verification in System-level Models and RTL. DAC 2007: 193-198
2006
15	EE	Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra: Sequential Equivalence Checking. VLSI Design 2006: 18-19
2005
14		Alfred Koelbl, Yuan Lu, Anmol Mathur: Embedded tutorial: formal equivalence checking between system-level models and RTL. ICCAD 2005: 965-971
2003
13	EE	G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja: Graph Transformations for Improved Tree Height Reduction. VLSI Design 2003: 474-479
2001
12	EE	Anmol Mathur, Sanjeev Saluja: Improved Merging of Datapath Operators using Information Content and Required Precision Analysis. DAC 2001: 462-467
1998
11	EE	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee: An Implicit Algorithm for Finding Steady States and its Application to FSM Verification. DAC 1998: 611-614
10	EE	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee: Efficient equivalence checking of multi-phase designs using retiming. ICCAD 1998: 557-562
9	EE	Anmol Mathur, Ali Dasdan, Rajesh K. Gupta: Rate analysis for embedded systems. ACM Trans. Design Autom. Electr. Syst. 3(3): 408-436 (1998)
8	EE	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee: Efficient equivalence checking of multi-phase designs using phase abstraction and retiming. ACM Trans. Design Autom. Electr. Syst. 3(4): 600-625 (1998)
1997
7	EE	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee: An Efficient Assertion Checker for Combinational Properties. DAC 1997: 734-739
6	EE	Ali Dasdan, Anmol Mathur, Rajesh K. Gupta: RATAN: A tool for rate analysis and rate constraint debugging for embedded systems. ED&TC 1997: 2-6
5	EE	Anmol Mathur, C. L. Liu: Timing-driven placement for regular architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 597-608 (1997)
1996
4		Anmol Mathur, Edward M. Reingold: Generalized Kraft's Inequality and Discrete k-Modal Search. SIAM J. Comput. 25(2): 420-447 (1996)
1995
3	EE	Anmol Mathur, K. C. Chen, C. L. Liu: Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. FPGA 1995: 118-124
2	EE	Anmol Mathur, K. C. Chen, C. L. Liu: Re-engineering of timing constrained placements for regular architectures. ICCAD 1995: 485-490
1994
1	EE	Anmol Mathur, C. L. Liu: Compression-relaxation: a new approach to performance driven placement for regular architectures. ICCAD 1994: 130-136

Coauthor Index

1	LaNae J. Avra	[13]
2	M. Balakrishnan	[15]
3	Prithviraj Banerjee (Prith Banerjee)	[7] [8] [10] [11]
4	Paul van Besouw	[13]
5	K. C. Chen	[2] [3]
6	Ali Dasdan	[6] [9]
7	Masahiro Fujita	[15]
8	Rajesh K. Gupta (Rajesh Gupta)	[6] [9]
9	Gagan Hasteer	[7] [8] [10] [11]
10	Alfred Koelbl	[14]
11	Venkat Krishnaswamy	[16]
12	C. L. Liu (Chung Laung (Dave) Liu)	[1] [2] [3] [5]
13	Yuan Lu	[14]
14	G. N. Mangalam	[13]
15	Raj S. Mitra	[15]
16	Sanjiv Narayan	[13]
17	Edward M. Reingold	[4]
18	Sanjeev Saluja	[12] [13]
19	Qi Wang	[17]

Colors in the list of coauthors