Markus Olbrich

2008
15	EE	Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl: Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI 2008: 17-22
14	EE	Markus Olbrich, Erich Barke: Distribution arithmetic for stochastical analysis. ASP-DAC 2008: 537-542
13	EE	Darius Grabowski, Markus Olbrich, Erich Barke: Analog circuit simulation using range arithmetics. ASP-DAC 2008: 762-767
12	EE	Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke: A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. DDECS 2008: 54-58
11	EE	S. Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt: Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). FDL 2008: 73-77
2007
10	EE	Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl: Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI 2007: 43-48
9	EE	Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke: Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. DAC 2007: 706-711
8	EE	M. Zhang, Markus Olbrich, D. Seider, M. Frerichs, H. Kinzelbach, Erich Barke: CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. DATE 2007: 243-248
7		Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke: Range Arithmetics to Speed up Reachability Analysis of Analog Systems. FDL 2007: 38-43
2005
6	EE	Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten: Routing of analog busses with parasitic symmetry. ISPD 2005: 14-19
2004
5	EE	Markus Olbrich, Erich Barke: Placement Using a Localization Probability Model (LPM). DATE 2004: 1412
4	EE	Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke: Wirelength Reduction Using 3-D Physical Design. PATMOS 2004: 453-462
2003
3		Andreas Hermann, Markus Olbrich, Erich Barke: Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. VLSI-SOC 2003: 13-18
2001
2	EE	Markus Olbrich, Achim Rein, Erich Barke: An improved hierarchical classification algorithm for structural analysis of integrated circuits. DATE 2001: 807
1998
1	EE	Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke: An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. FPL 1998: 79-88

Coauthor Index

1	Erich Barke	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
2	Volker Meyer zu Bexten	[6]
3	Markus Bühler	[15]
4	M. Frerichs	[8]
5	Darius Grabowski	[7] [13]
6	Christoph Grimm	[7]
7	Klaus Harbich	[1]
8	Hedi Harizi	[9]
9	Robert HauBler	[9]
10	Andreas Hermann	[3]
11	S. Hoelldampf	[11]
12	Thomas Jambor	[12]
13	Idris Kaya	[4]
14	H. Kinzelbach	[8]
15	Jürgen Koehl	[10] [15]
16	Ingmar Neumann	[11]
17	Philipp V. Panitz	[10] [15]
18	Achim Rein	[2]
19	Silke Salewski	[4]
20	Sebastian Schmidt	[11]
21	Lars A. Schreiner	[6]
22	D. Seider	[8]
23	Jörn Stohmann	[1]
24	Daniel Zaum	[11] [12]
25	M. Zhang	[8]