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Markus Olbrich

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2008
15EEPhilipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl: Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI 2008: 17-22
14EEMarkus Olbrich, Erich Barke: Distribution arithmetic for stochastical analysis. ASP-DAC 2008: 537-542
13EEDarius Grabowski, Markus Olbrich, Erich Barke: Analog circuit simulation using range arithmetics. ASP-DAC 2008: 762-767
12EEThomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke: A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. DDECS 2008: 54-58
11EES. Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt: Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). FDL 2008: 73-77
2007
10EEPhilipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl: Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI 2007: 43-48
9EEHedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke: Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. DAC 2007: 706-711
8EEM. Zhang, Markus Olbrich, D. Seider, M. Frerichs, H. Kinzelbach, Erich Barke: CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. DATE 2007: 243-248
7 Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke: Range Arithmetics to Speed up Reachability Analysis of Analog Systems. FDL 2007: 38-43
2005
6EELars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten: Routing of analog busses with parasitic symmetry. ISPD 2005: 14-19
2004
5EEMarkus Olbrich, Erich Barke: Placement Using a Localization Probability Model (LPM). DATE 2004: 1412
4EEIdris Kaya, Silke Salewski, Markus Olbrich, Erich Barke: Wirelength Reduction Using 3-D Physical Design. PATMOS 2004: 453-462
2003
3 Andreas Hermann, Markus Olbrich, Erich Barke: Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. VLSI-SOC 2003: 13-18
2001
2EEMarkus Olbrich, Achim Rein, Erich Barke: An improved hierarchical classification algorithm for structural analysis of integrated circuits. DATE 2001: 807
1998
1EEJörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke: An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. FPL 1998: 79-88

Coauthor Index

1Erich Barke [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
2Volker Meyer zu Bexten [6]
3Markus Bühler [15]
4M. Frerichs [8]
5Darius Grabowski [7] [13]
6Christoph Grimm [7]
7Klaus Harbich [1]
8Hedi Harizi [9]
9Robert HauBler [9]
10Andreas Hermann [3]
11S. Hoelldampf [11]
12Thomas Jambor [12]
13Idris Kaya [4]
14H. Kinzelbach [8]
15Jürgen Koehl [10] [15]
16Ingmar Neumann [11]
17Philipp V. Panitz [10] [15]
18Achim Rein [2]
19Silke Salewski [4]
20Sebastian Schmidt [11]
21Lars A. Schreiner [6]
22D. Seider [8]
23Jörn Stohmann [1]
24Daniel Zaum [11] [12]
25M. Zhang [8]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)