| 2008 |
|---|
| 18 | EE | Juanjo Noguera,
Robert Esser,
Katarina Paulsson,
Michael Hübner,
Jürgen Becker:
Towards Novel Approaches in Design Automation for FPGA Power Optimization.
PATMOS 2008: 419-428 |
| 2007 |
|---|
| 17 | EE | Sudarshan Banerjee,
Elaheh Bozorgzadeh,
Nikil Dutt,
Juanjo Noguera:
Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.
DAC 2007: 771-776 |
| 16 | EE | Juanjo Noguera,
Irwin O. Kennedy:
Power Reduction in Network Equipment through Adaptive Partial Reconfiguration.
FPL 2007: 240-245 |
| 2006 |
|---|
| 15 | EE | Juanjo Noguera,
Luis Baldez,
Narcis Simon,
Lluis Abello:
Software-friendly HW/SW co-simulation: an industrial case study.
DATE Designers' Forum 2006: 100-105 |
| 14 | EE | Juanjo Noguera,
Rosa M. Badia:
System-level power-performance tradeoffs for reconfigurable computing.
IEEE Trans. VLSI Syst. 14(7): 730-739 (2006) |
| 2005 |
|---|
| 13 | | Zexin Pan,
Juanjo Noguera,
B. Earl Wells:
Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures.
ERSA 2005: 182-188 |
| 12 | | Juanjo Noguera,
Rosa M. Badia:
Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures.
FPL 2005: 563-567 |
| 2004 |
|---|
| 11 | EE | Juanjo Noguera,
Rosa M. Badia:
Power-performance trade-offs for reconfigurable computing.
CODES+ISSS 2004: 116-121 |
| 10 | EE | Juanjo Noguera,
Rosa M. Badia:
Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling.
ACM Trans. Embedded Comput. Syst. 3(2): 385-406 (2004) |
| 2003 |
|---|
| 9 | EE | Juanjo Noguera,
Rosa M. Badia:
System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures.
CASES 2003: 73-83 |
| 2002 |
|---|
| 8 | EE | Juanjo Noguera,
Rosa M. Badia:
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures.
CODES 2002: 205-210 |
| 7 | EE | Juanjo Noguera,
Rosa M. Badia:
HW/SW codesign techniques for dynamically reconfigurable architectures.
IEEE Trans. VLSI Syst. 10(4): 399-415 (2002) |
| 2001 |
|---|
| 6 | EE | Juanjo Noguera,
Rosa M. Badia:
A HW/SW partitioning algorithm for dynamically reconfigurable architectures.
DATE 2001: 729 |
| 2000 |
|---|
| 5 | EE | Juanjo Noguera,
Rosa M. Badia:
Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers.
FPL 2000: 842-845 |
| 4 | EE | Josep Solé-Pareta,
Davide Careglio,
Salvatore Spadaro,
Jaume Masip Torner,
Juanjo Noguera,
Gabriel Junyent:
Modelling and Performance Evaluation of a National Scale Switchless Based Network.
INTERWORKING 2000: 337-347 |
| 3 | EE | Juanjo Noguera,
Rosa M. Badia:
Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures.
ISSS 2000: 100-106 |
| 1999 |
|---|
| 2 | EE | Juanjo Noguera,
Rosa M. Badia,
Jordi Domingo-Pascual,
Josep Solé-Pareta:
Reconfigurable Computing: An Innovative Solution for Multimedia and Telecommunication Networks Simulation.
EUROMICRO 1999: 2367-2374 |
| 1 | | Juanjo Noguera,
Rosa M. Badia,
Jordi Domingo-Pascual,
Josep Solé-Pareta:
A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation.
FPL 1999: 456-461 |
