| 2008 |
|---|
| 59 | EE | Younghyun Kim,
Youngjin Cho,
Naehyuck Chang,
Chaitali Chakrabarti,
Nam Ik Cho:
Extending the lifetime of media recorders constrained by battery and flash memory size.
ISLPED 2008: 159-164 |
| 58 | EE | Mark Woh,
Yuan Lin,
Sangwon Seo,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Richard Bruce,
Danny Kershaw,
Alastair Reid,
Mladen Wilder,
Krisztián Flautner:
From SODA to scotch: The evolution of a wireless baseband processor.
MICRO 2008: 152-163 |
| 57 | EE | Kyungsoo Lee,
Naehyuck Chang,
Jianli Zhuo,
Chaitali Chakrabarti,
Sudheendra Kadri,
Sarma B. K. Vrudhula:
A fuel-cell-battery hybrid for portable embedded systems.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 56 | EE | Jianli Zhuo,
Chaitali Chakrabarti:
Energy-efficient dynamic task scheduling algorithms for DVS systems.
ACM Trans. Embedded Comput. Syst. 7(2): (2008) |
| 2007 |
|---|
| 55 | EE | Jianli Zhuo,
Chaitali Chakrabarti,
Kyungsoo Lee,
Naehyuck Chang:
Dynamic Power Management with Hybrid Power Sources.
DAC 2007: 871-876 |
| 54 | EE | Jungsub Kim,
Prasanth Mangalagiri,
Kevin M. Irick,
Mahmut T. Kandemir,
Vijay Narayanan,
K. Sobti,
Lanping Deng,
Chaitali Chakrabarti,
Nikos Pitsianis,
Xiaobai Sun:
TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms.
FPL 2007: 68-73 |
| 53 | EE | Georgios Karakonstantis,
Nilanjan Banerjee,
Kaushik Roy,
Chaitali Chakrabarti:
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering.
ICCAD 2007: 199-204 |
| 52 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula,
Chaitali Chakrabarti:
Throughput of multi-core processors under thermal constraints.
ISLPED 2007: 201-206 |
| 51 | EE | Jianli Zhuo,
Chaitali Chakrabarti,
Naehyuck Chang:
Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source.
ISLPED 2007: 322-327 |
| 50 | EE | Mark Woh,
Sangwon Seo,
Hyunseok Lee,
Yuan Lin,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Krisztián Flautner:
The Next Generation Challenge for Software Defined Radio.
SAMOS 2007: 343-354 |
| 49 | EE | Yuan Lin,
Hyunseok Lee,
Mark Woh,
Yoav Harel,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Krisztián Flautner:
SODA: A High-Performance DSP Architecture for Software-Defined Radio.
IEEE Micro 27(1): 114-123 (2007) |
| 48 | EE | Ye Li,
Bertan Bakkaloglu,
Chaitali Chakrabarti:
A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends.
IEEE Trans. VLSI Syst. 15(1): 90-103 (2007) |
| 47 | EE | Sung-Hoon Oh,
Hang Song,
James T. Aberle,
Bertan Bakkaloglu,
Chaitali Chakrabarti:
Automatic antenna-tuning unit for software-defined and cognitive radio.
Wireless Communications and Mobile Computing 7(9): 1103-1115 (2007) |
| 2006 |
|---|
| 46 | EE | Jianli Zhuo,
Chaitali Chakrabarti,
Naehyuck Chang,
Sarma B. K. Vrudhula:
Extending the lifetime of fuel cell based hybrid systems.
DAC 2006: 562-567 |
| 45 | EE | Youngjin Cho,
Naehyuck Chang,
Chaitali Chakrabarti,
Sarma B. K. Vrudhula:
High-level power management of embedded systems with application-specific energy cost functions.
DAC 2006: 568-573 |
| 44 | EE | Yuan Lin,
Hyunseok Lee,
Mark Woh,
Yoav Harel,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Krisztián Flautner:
SODA: A Low-power Architecture For Software Radio.
ISCA 2006: 89-101 |
| 43 | EE | Hyunseok Lee,
Trevor N. Mudge,
Chaitali Chakrabarti:
Reducing idle mode power in software defined radio terminals.
ISLPED 2006: 101-106 |
| 42 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula,
Chaitali Chakrabarti,
Naehyuck Chang:
An optimal analytical solution for processor speed control with thermal constraints.
ISLPED 2006: 292-297 |
| 41 | EE | Jianli Zhuo,
Chaitali Chakrabarti,
Naehyuck Chang,
Sarma B. K. Vrudhula:
Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids.
ISLPED 2006: 424-429 |
| 40 | EE | Rahim Khoja,
Mehul Marolia,
Tinku Acharya,
Chaitali Chakrabarti:
A coprocessor architecture for fast protein structure prediction.
Pattern Recognition 39(12): 2494-2505 (2006) |
| 39 | EE | Tinku Acharya,
Chaitali Chakrabarti:
A Survey on Lifting-based Discrete Wavelet Transform Architectures.
VLSI Signal Processing 42(3): 321-339 (2006) |
| 2005 |
|---|
| 38 | EE | Jianli Zhuo,
Chaitali Chakrabarti:
An efficient dynamic task scheduling algorithm for battery powered DVS systems.
ASP-DAC 2005: 846-849 |
| 37 | EE | Jianli Zhuo,
Chaitali Chakrabarti:
System-level energy-efficient dynamic task scheduling.
DAC 2005: 628-631 |
| 2004 |
|---|
| 36 | | Hafijur Rahman,
Chaitali Chakrabarti:
A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage.
ISCAS (2) 2004: 297-300 |
| 35 | | Sumant Bhutoria,
Chaitali Chakrabarti:
Parameterized SoC design for portable systems.
ISCAS (2) 2004: 449-452 |
| 34 | | Jameel Ahmed,
Chaitali Chakrabarti:
A dynamic task scheduling algorithm for battery powered DVS systems.
ISCAS (2) 2004: 813-816 |
| 33 | EE | Ali Manzak,
Chaitali Chakrabarti:
Optimum Buffer Size for Dynamic Voltage Processors.
PATMOS 2004: 711-721 |
| 32 | EE | Todd M. Austin,
David Blaauw,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Wayne Wolf:
Mobile Supercomputers.
IEEE Computer 37(5): 81-83 (2004) |
| 2003 |
|---|
| 31 | | Kishore Andra,
Chaitali Chakrabarti,
Tinku Acharya:
A high-performance JPEG2000 architecture.
IEEE Trans. Circuits Syst. Video Techn. 13(3): 209- (2003) |
| 30 | EE | Ali Manzak,
Chaitali Chakrabarti:
Variable voltage task scheduling algorithms for minimizing energy/power.
IEEE Trans. VLSI Syst. 11(2): 270-276 (2003) |
| 2002 |
|---|
| 29 | EE | Daler N. Rakhmatov,
Sarma B. K. Vrudhula,
Chaitali Chakrabarti:
Battery-conscious task sequencing for portable devices including voltage/clock scaling.
DAC 2002: 189-194 |
| 28 | EE | Kishore Andra,
Chaitali Chakrabarti,
Tinku Acharya:
A high performance JPEG2000 architecture.
ISCAS (1) 2002: 765-768 |
| 27 | EE | Rusell E. Henning,
Chaitali Chakrabarti:
Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations.
ISLPED 2002: 68-71 |
| 2001 |
|---|
| 26 | EE | Sathishkumar Udayanarayanan,
Chaitali Chakrabarti:
Address Code Generation for Digital Signal Processors.
DAC 2001: 353-358 |
| 25 | | Ali Manzak,
Chaitali Chakrabarti:
Voltage Scaling for Energy Minimization with QoS Constraints.
ICCD 2001: 438-446 |
| 24 | EE | Ali Manzak,
Chaitali Chakrabarti:
Variable voltage task scheduling algorithms for minimizing energy.
ISLPED 2001: 279-282 |
| 23 | EE | Wen-Tsong Shiue,
Sathishkumar Udayanarayanan,
Chaitali Chakrabarti:
Data memory design and exploration for low-power embedded systems.
ACM Trans. Design Autom. Electr. Syst. 6(4): 553-568 (2001) |
| 2000 |
|---|
| 22 | | Kishore Andra,
Tinku Acharya,
Chaitali Chakrabarti:
A Multi-Bit Binary Arithmetic Coding Technique.
ICIP 2000 |
| 21 | EE | Sathishkumar Udayanarayanan,
Chaitali Chakrabarti:
Energy-efficient code generation for DSP56000 family (poster session).
ISLPED 2000: 247-249 |
| 20 | EE | Russell Henning,
Chaitali Chakrabarti:
Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design.
VLSI Design 2000: 38-43 |
| 19 | EE | Chaitali Chakrabarti,
Lori E. Lucke:
VLSI architectures for weighted order statistic (WOS) filters.
Signal Processing 80(8): 1419-1433 (2000) |
| 1999 |
|---|
| 18 | EE | Wen-Tsong Shiue,
Chaitali Chakrabarti:
Memory Exploration for Low Power, Embedded Systems.
DAC 1999: 140-145 |
| 17 | EE | Wen-Tsong Shiue,
Chaitali Chakrabarti:
Memory exploration for low power embedded systems.
ISCAS (1) 1999: 250-253 |
| 16 | EE | Ali Manzak,
Chaitali Chakrabarti:
A low power scheduling scheme with resources operating at multiple voltages.
ISCAS (1) 1999: 354-357 |
| 1997 |
|---|
| 15 | | Rusell E. Henning,
Chaitali Chakrabarti:
High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder.
ICCD 1997: 571-576 |
| 1996 |
|---|
| 14 | EE | Hsiang-Ling Li,
Chaitali Chakrabarti:
Motion estimation of two-dimensional objects based on the straight line hough transform: A new approach.
Pattern Recognition 29(8): 1245-1258 (1996) |
| 13 | EE | Chaitali Chakrabarti,
Mohan Vishwanath,
Robert Michael Owens:
Architectures for wavelet transforms: A survey.
VLSI Signal Processing 14(2): 171-192 (1996) |
| 1995 |
|---|
| 12 | EE | Kala Srivatsan,
Chaitali Chakrabarti,
Lori Lucke:
Low power data format converter design using semi-static register allocation.
ICCD 1995: 460-465 |
| 11 | | Hsiang-Ling Li,
Chaitali Chakrabarti:
A New Viterbi Decoder Design for Code Rate K/N.
ISCAS 1995: 549-552 |
| 10 | EE | Lori Lucke,
Chaitali Chakrabarti:
A digit-serial architecture for gray-scale morphological filtering.
IEEE Transactions on Image Processing 4(3): 387-391 (1995) |
| 1994 |
|---|
| 9 | | Chaitali Chakrabarti,
Lori Lucke:
Efficient Architectures for Hidden Surface Removal.
ICIP (1) 1994: 661-665 |
| 8 | | Srikanth Karkada,
Chaitali Chakrabarti,
Andreas Spanias:
High Sample Rate Architectures for Block Adaptive Filters.
ISCAS 1994: 131-134 |
| 7 | | Lori Lucke,
Chaitali Chakrabarti:
A Digit-Serial Architecture for Gray-Scale Morphological Filtering.
ISCAS 1994: 207-210 |
| 6 | | Gagan Gupta,
Chaitali Chakrabarti:
VLSI Architectures for Hierarchical Block Matching.
ISCAS 1994: 215-218 |
| 5 | | Chaitali Chakrabarti,
Li-Yu Wang:
Novel Sorting Netowrk-Based Architectures for Rank Order Filters.
ISCAS 1994: 89-93 |
| 4 | EE | Chaitali Chakrabarti,
Li-Yu Wang:
Novel sorting network-based architectures for rank order filters.
IEEE Trans. VLSI Syst. 2(4): 502-507 (1994) |
| 1993 |
|---|
| 3 | | Chaitali Chakrabarti:
Efficient stack filter implementations of rank order filters.
ISCAS 1993: 958-961 |
| 1991 |
|---|
| 2 | | Chaitali Chakrabarti,
Joseph JáJá:
VLSI Architectures for Multidimensional Transforms.
IEEE Trans. Computers 40(9): 1053-1057 (1991) |
| 1990 |
|---|
| 1 | | Chaitali Chakrabarti,
Joseph JáJá:
Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition.
IEEE Trans. Computers 39(11): 1359-1368 (1990) |
