2007 |
14 | EE | Francine Bacchini,
Greg Spirakis,
Juan Antonio Carballo,
Kurt Keutzer,
Aart J. de Geus,
Fu-Chieh Hsu,
Kazu Yamada:
Megatrends and EDA 2017.
DAC 2007: 21-22 |
13 | EE | Aart J. de Geus:
A. Richard Newton: Technologist with a Mission.
IEEE Design & Test of Computers 24(1): 6-7 (2007) |
2005 |
12 | EE | Jay Vleeschhouwer,
Warren East,
Michael J. Fister,
Aart J. de Geus,
Walden C. Rhines,
Jackson Hu,
Rick Cassidy:
Differentiate and deliver: leveraging your partners.
DAC 2005: 1 |
2004 |
11 | EE | Robert Dahlberg,
Kurt Keutzer,
R. Bingham,
Aart J. de Geus,
Walden C. Rhines:
EDA: this is serious business.
DAC 2004: 1 |
2002 |
10 | EE | Aart J. de Geus:
Electronic Industry on Fire: How to Survive and Thrive.
VLSI Design 2002: 6 |
2000 |
9 | EE | Aart J. de Geus:
Slap it Together and Ship it!
ISQED 2000: 23-24 |
1994 |
8 | EE | Joseph B. Costello,
Walden C. Rhines,
Aart J. de Geus,
Alain Hanover,
Doug Fairbairn,
Rick Carlson,
Ronald Collett:
Executive Perspective and Vision of the Future of EDA (Panel).
DAC 1994: 48 |
7 | | Aart J. de Geus:
Test: The New Value-Added Field.
ITC 1994: 12 |
1992 |
6 | | Aart J. de Geus:
High Level Design: A Design Vision for the 90's.
ICCD 1992: 8 |
5 | EE | Allen Dewey,
Aart J. de Geus:
VHDL: Toward a Unified View of Design.
IEEE Design & Test of Computers 9(2): 8-17 (1992) |
1987 |
4 | EE | Robert Lisanke,
Franc Brglez,
Aart J. de Geus,
David Gregory:
Testability-Driven Random Test-Pattern Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 1082-1087 (1987) |
1986 |
3 | EE | Aart J. de Geus:
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference.
DAC 1986: 78 |
2 | EE | David Gregory,
Karen A. Bartlett,
Aart J. de Geus,
Gary D. Hachtel:
SOCRATES: a system for automatically synthesizing and optimizing combinational logic.
DAC 1986: 79-85 |
1 | EE | Karen A. Bartlett,
William W. Cohen,
Aart J. de Geus,
Gary D. Hachtel:
Synthesis and Optimization of Multilevel Logic under Timing Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 582-596 (1986) |