| 2008 |
|---|
| 4 | EE | Zhanyuan Jiang,
Weiping Shi:
Circuit-wise buffer insertion and gate sizing algorithm with scalability.
DAC 2008: 708-713 |
| 2007 |
|---|
| 3 | EE | Zhanyuan Jiang,
Shiyan Hu,
Weiping Shi:
A New Twisted Differential Line Structure in Global Bus Design.
DAC 2007: 180-183 |
| 2 | EE | Zhanyuan Jiang,
Shiyan Hu,
Jiang Hu,
Weiping Shi:
An Efficient Algorithm for RLC Buffer Insertion.
ISQED 2007: 171-175 |
| 2006 |
|---|
| 1 | EE | Zhanyuan Jiang,
Shiyan Hu,
Jiang Hu,
Zhuo Li,
Weiping Shi:
A new RLC buffer insertion algorithm.
ICCAD 2006: 553-557 |
