2009 | ||
---|---|---|
32 | EE | Albert Sidelnik, I-Jui Sung, Wanmin Wu, María Jesús Garzarán, Wen-mei W. Hwu, Klara Nahrstedt, David A. Padua, Sanjay J. Patel: Optimization of tele-immersion codes. GPGPU 2009: 85-93 |
2008 | ||
31 | EE | Aqeel Mahesri, Daniel Johnson, Neal Crago, Sanjay J. Patel: Tradeoffs in designing accelerator architectures for visual computing. MICRO 2008: 164-175 |
2007 | ||
30 | EE | Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel: Implicitly Parallel Programming Models for Thousand-Core Microprocessors. DAC 2007: 754-759 |
29 | EE | Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman: ParallAX: an architecture for real-time physics. ISCA 2007: 232-243 |
28 | EE | Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel: Examining ACE analysis reliability estimates using fault-injection. ISCA 2007: 460-469 |
27 | EE | Thomas Y. Yeh, Petros Faloutsos, Milos Ercegovac, Sanjay J. Patel, Glenn Reinman: The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. MICRO 2007: 394-406 |
2006 | ||
26 | EE | Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Jose (Nacho) Navarro, Wen-mei W. Hwu: Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. IEEE Trans. Computers 55(1): 18-33 (2006) |
25 | EE | Nicholas J. Wang, Sanjay J. Patel: ReStore: Symptom-Based Soft Error Detection in Microprocessors. IEEE Trans. Dependable Sec. Comput. 3(3): 188-201 (2006) |
2005 | ||
24 | EE | Nicholas J. Wang, Sanjay J. Patel: ReStore: Symptom Based Soft Error Detection in Microprocessors. DSN 2005: 30-39 |
23 | Wen-mei W. Hwu, Sanjay J. Patel: The Future of Computer Architecture Research: An Industrial Perspective. HPCA 2005: 264 | |
22 | EE | Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steven S. Lumetta: Continuous Optimization. ISCA 2005: 86-97 |
21 | EE | Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer: An Experimental Study of Soft Errors in Microprocessors. IEEE Micro 25(6): 30-39 (2005) |
2004 | ||
20 | EE | Nicholas J. Wang, Justin Quek, Todd M. Rafacz, Sanjay J. Patel: Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline. DSN 2004: 61- |
19 | EE | Todd E. Ehrhart, Sanjay J. Patel: Reducing the Scheduling Critical Cycle Using Wakeup Prediction. HPCA 2004: 222-231 |
2003 | ||
18 | EE | Francesco Spadini, Brian Fahs, Sanjay J. Patel, Steven S. Lumetta: Improving Quasi-Dynamic Schedules through Region Slip. CGO 2003: 149-158 |
17 | EE | Brian Slechta, David Crowe, Brian Fahs, Michael Fertig, Gregory A. Muthler, Justin Quek, Francesco Spadini, Sanjay J. Patel, Steven Lumetta: Dynamic Optimization of Micro-Operations. HPCA 2003: 165- |
16 | EE | Nicholas J. Wang, Michael Fertig, Sanjay J. Patel: Y-Branches: When You Come to a Fork in the Road, Take It. IEEE PACT 2003: 56- |
15 | EE | Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu: Beating in-order stalls with "flea-flicker" two-pass pipelining. MICRO 2003: 387-398 |
14 | EE | Steven Lumetta, Sanjay J. Patel: Characterization of essential dynamic instructions. SIGMETRICS 2003: 308-309 |
2002 | ||
13 | EE | Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta: Instruction fetch deferral using static slack. MICRO 2002: 51-61 |
2001 | ||
12 | EE | Brian Fahs, Satarupa Bose, Matthew M. Crum, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, Steven S. Lumetta: Performance characterization of a hardware mechanism for dynamic optimization. MICRO 2001: 16-27 |
11 | EE | Sanjay J. Patel, Steven Lumetta: rePLay: A Hardware Framework for Dynamic Optimization. IEEE Trans. Computers 50(6): 590-608 (2001) |
2000 | ||
10 | EE | Sanjay J. Patel, Tony Tung, Satarupa Bose, Matthew M. Crum: Increasing the size of atomic instruction blocks using control flow assertions. MICRO 2000: 303-313 |
1999 | ||
9 | EE | Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt: Evaluation of Design Options for the Trace Cache Fetch Mechanism. IEEE Trans. Computers 48(2): 193-204 (1999) |
1998 | ||
8 | EE | Sanjay J. Patel, Marius Evers, Yale N. Patt: Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ISCA 1998: 262-271 |
7 | EE | Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt: An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. ISCA 1998: 52-61 |
6 | EE | Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt: Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors. MICRO 1998: 173-181 |
1997 | ||
5 | EE | Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt: Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. MICRO 1997: 24-33 |
4 | Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark: One Billion Transistors, One Uniprocessor, One Chip. IEEE Computer 30(9): 51-57 (1997) | |
1994 | ||
3 | Dina L. McKinney, Daniel L. Leibholz, Mark B. Rosenbluth, James R. Mullens, Kwong-Tak A. Chui, Masooma Bhaiwala, Sanjay J. Patel, Christopher L. Houghton, Delvan A. Ramey: DECchip 21066: The Alpha AXP Chip for Cost-Focused Systems. COMPCON 1994: 406-413 | |
2 | Dina L. McKinney, Masooma Bhaiwala, Kwong-Tak A. Chui, Christopher L. Houghton, James R. Mullens, Daniel L. Leibholz, Sanjay J. Patel, Delvan A. Ramey, Mark B. Rosenbluth: Digital;s DECchip 21066: The First Cost-focused Alpha AXP Chip Digital Technical Journal 6(1): 0- (1994) | |
1986 | ||
1 | EE | Sanjay J. Patel, Janak H. Patel: Effectiveness of heuristics measures for automatic test pattern generation. DAC 1986: 547-552 |