| 2009 |
|---|
| 7 | EE | Alessandro Cevrero,
Panagiotis Athanasopoulos,
Hadi Parandeh-Afshar,
Philip Brisk,
Yusuf Leblebici,
Paolo Ienne,
Maurizio Skerlj:
3D configuration caching for 2D FPGAs.
FPGA 2009: 286 |
| 2008 |
|---|
| 6 | EE | Hadi Parandeh-Afshar,
Philip Brisk,
Paolo Ienne:
Efficient synthesis of compressor trees on FPGAs.
ASP-DAC 2008: 138-143 |
| 5 | EE | Hadi Parandeh-Afshar,
Philip Brisk,
Paolo Ienne:
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming.
DATE 2008: 1256-1261 |
| 4 | EE | Hadi Parandeh-Afshar,
Philip Brisk,
Paolo Ienne:
A novel FPGA logic block for improved arithmetic performance.
FPGA 2008: 171-180 |
| 3 | EE | Alessandro Cevrero,
Panagiotis Athanasopoulos,
Hadi Parandeh-Afshar,
Ajay K. Verma,
Philip Brisk,
Frank K. Gürkaynak,
Yusuf Leblebici,
Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.
FPGA 2008: 181-190 |
| 2007 |
|---|
| 2 | EE | Philip Brisk,
Ajay K. Verma,
Paolo Ienne,
Hadi Parandeh-Afshar:
Enhancing FPGA Performance for Arithmetic Circuits.
DAC 2007: 334-337 |
| 2006 |
|---|
| 1 | EE | Hadi Parandeh-Afshar,
Ali Afzali-Kusha,
Ali Khakifirooz:
A very high performance address BUS encoder.
ISCAS 2006 |
