| 2007 |
|---|
| 5 | EE | Shady Copty,
Itai Jaeger,
Yoav Katz,
Michael Vinov:
Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation.
DAC 2007: 891-895 |
| 2006 |
|---|
| 4 | | Yehuda Naveh,
Michal Rimon,
Itai Jaeger,
Yoav Katz,
Michael Vinov,
Eitan Marcus,
Gil Shurek:
Constraint-Based Random Stimuli Generation for Hardware Verification.
AAAI 2006 |
| 2005 |
|---|
| 3 | EE | Allon Adir,
Yaron Arbetman,
Bella Dubrov,
Yossi Lichtenstein,
Michal Rimon,
Michael Vinov,
Massimo A. Calligaro,
Andrew Cofler,
Gabriel Duffy:
VLIW: a case study of parallelism verification.
DAC 2005: 779-782 |
| 2004 |
|---|
| 2 | EE | Michael L. Behm,
John M. Ludden,
Yossi Lichtenstein,
Michal Rimon,
Michael Vinov:
Industrial experience with test generation languages for processor verification.
DAC 2004: 36-40 |
| 1 | EE | Allon Adir,
Eli Almog,
Laurent Fournier,
Eitan Marcus,
Michal Rimon,
Michael Vinov,
Avi Ziv:
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification.
IEEE Design & Test of Computers 21(2): 84-93 (2004) |
