| 2008 |
|---|
| 7 | EE | Abinash Roy,
Masud H. Chowdhury:
Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects.
ISCAS 2008: 2426-2429 |
| 6 | EE | Jingye Xu,
Abinash Roy,
Masud H. Chowdhury:
Optimization technique for flip-flop inserted global interconnect.
ISCAS 2008: 3386-3389 |
| 2007 |
|---|
| 5 | EE | Abinash Roy,
Noha Mahmoud,
Masud H. Chowdhury:
Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew.
DAC 2007: 184-187 |
| 4 | EE | Jingye Xu,
Abinash Roy,
Masud H. Chowdhury:
Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining.
DATE 2007: 1218-1223 |
| 3 | EE | Jingye Xu,
Abinash Roy,
Masud H. Chowdhury:
Power Consumption Analysis of Flip-flop Based Interconnect Pipelining.
ISCAS 2007: 3716-3719 |
| 2 | EE | Abinash Roy,
Noha Mahmoud,
Masud H. Chowdhury:
Delay and Clock Skew Variation due to Coupling Capacitance and Inductance.
ISCAS 2007: 621-624 |
| 1 | EE | Abinash Roy,
Masud H. Chowdhury:
Global Interconnect Optimization in the Presence of On-chip Inductance.
ISCAS 2007: 885-888 |
