| |
| 2007 | ||
|---|---|---|
| 2 | EE | Anmol Mathur, Venkat Krishnaswamy: Design for Verification in System-level Models and RTL. DAC 2007: 193-198 |
| 2006 | ||
| 1 | EE | Philippe Georgelin, Venkat Krishnaswamy: Towards a C++-based design methodology facilitating sequential equivalence checking. DAC 2006: 93-96 |
| 1 | Philippe Georgelin | [1] |
| 2 | Anmol Mathur | [2] |