2009 |
42 | EE | Shu-Hsuan Chou,
Che-Neng Wen,
Yan-Ling Liu,
Tien-Fu Chen:
VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models.
ISQED 2009: 535-540 |
2008 |
41 | EE | Kuei-Chung Chang,
Jih-Sheng Shen,
Tien-Fu Chen:
Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
2007 |
40 | EE | Jui-Chin Chu,
Wei-Chun Ku,
Shu-Hsuan Chou,
Tien-Fu Chen,
Jiun-In Guo:
An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model.
DAC 2007: 652-657 |
39 | EE | Chang-Ching Yeh,
Kuei-Chung Chang,
Tien-Fu Chen,
Chingwei Yeh:
Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling.
HiPEAC 2007: 105-119 |
38 | EE | Kuei-Chung Chang,
Tien-Fu Chen:
Efficient segment-based video transcoding proxy for mobile multimedia services.
Journal of Systems Architecture 53(11): 833-845 (2007) |
2006 |
37 | EE | Kuei-Chung Chang,
Jih-Sheng Shen,
Tien-Fu Chen:
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs.
DAC 2006: 143-148 |
36 | | Kuei-Chung Chang,
Jih-Sheng Shen,
Tien-Fu Chen:
Fast Run-Time Power Monitoring Methodology for Embedded Systems.
ESA 2006: 129-133 |
35 | EE | Wei-Chun Ku,
Shu-Hsuan Chou,
Jui-Chin Chu,
Chih-Heng Kang,
Tien-Fu Chen,
Jiun-In Guo:
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications.
ICME 2006: 25-28 |
34 | EE | Jui-Chin Chu,
Chih-Wen Huang,
He-Chun Chen,
Keng-Po Lu,
Ming-Shuan Lee,
Jiun-In Guo,
Tien-Fu Chen:
Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications.
ISCAS 2006 |
33 | EE | Jih-Sheng Shen,
Kuei-Chung Chang,
Tien-Fu Chen:
On a design of crossroad switches for low-power on-chip communication architectures.
ISCAS 2006 |
2005 |
32 | | Kuei-Chung Chang,
Jih-Sheng Shen,
Tien-Fu Chen:
Crossroad System-on-Chip Communication Architecture for Low Power Embedded Systems.
ESA 2005: 151-157 |
31 | EE | Kuei-Chung Chang,
Ren-Yo Wu,
Tien-Fu Chen:
Efficient Segment-Based Video Transcoding Proxy for Mobile Multimedia Services.
ICME 2005: 755-758 |
30 | EE | Kuei-Chung Chang,
Jih-Sheng Shen,
Tien-Fu Chen:
A low-power crossroad switch architecture and its core placement for network-on-chip.
ISLPED 2005: 375-380 |
29 | | Kuei-Chung Chang,
Tien-Fu Chen,
Wei-Yen Chuang:
System-Level Power-Aware Scheduling by Operation-based Prediction.
PSC 2005: 154-160 |
28 | EE | Chih-wen Hsueh,
Tien-Fu Chen,
Rong-Guey Chang,
Shi-Wu Lo:
Development of Architecture and Software Technologies in High-Performance Low-Power SoC Design.
RTCSA 2005: 475-480 |
27 | EE | Tien-Fu Chen,
Chia-Ming Hsu,
S.-R. Wu:
Flexible Heterogeneous Multicore Architectures for Versatile Media Processing Via Customized Long Instruction Words.
IEEE Trans. Circuits Syst. Video Techn. 15(5): 659-672 (2005) |
2004 |
26 | | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang,
Ching-Wei Yeh,
Tien-Fu Chen:
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms.
ISCAS (2) 2004: 141-144 |
25 | | Tien-Fu Chen,
Tsung-Ming Hsieh,
Chun-Li Wei:
Unified bus encoding by stream reconstruction with variable strides.
ISCAS (2) 2004: 329-332 |
24 | | Rei-Chin Ju,
Jia-Wei Chen,
Jiun-In Guo,
Tien-Fu Chen:
A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT.
ISCAS (2) 2004: 769-772 |
23 | EE | Chih-Da Chien,
Chien-Chang Lin,
Jiun-In Guo,
Tien-Fu Chen:
A power-aware IP core generator for the one-dimensional discrete Fourier transform.
ISCAS (3) 2004: 637-640 |
22 | EE | Hao-Ran Liu,
Tien-Fu Chen:
Scalable locality-aware event dispatching mechanism for network servers.
IEE Proceedings - Software 151(3): 129-138 (2004) |
21 | EE | Yung-Cheng Ma,
Tien-Fu Chen,
Chung-Ping Chung:
Branch-and-bound task allocation with task clustering-based pruning.
J. Parallel Distrib. Comput. 64(11): 1223-1240 (2004) |
2003 |
20 | | Wann-Yun Shieh,
Tien-Fu Chen,
Chung-Ping Chung:
A Tree-Based inverted File for Fast Ranked-Document Retrieval.
IKE 2003: 64-69 |
19 | | Chia-Ming Hsu,
Tien-Fu Chen:
Flexible Heterogeneous Multicore Architectures for Media Processing via Customized Long Instruction Words.
VLSI-SOC 2003: 270-275 |
18 | EE | Hao-Ran Liu,
Tien-Fu Chen:
A Scalable Locality-Aware Event Dispatching Mechanism for Network Servers.
WWW (Posters) 2003 |
17 | EE | Wann-Yun Shieh,
Tien-Fu Chen,
Jean Jyh-Jiun Shann,
Chung-Ping Chung:
Inverted file compression through document identifier reassignment.
Inf. Process. Manage. 39(1): 117-131 (2003) |
16 | EE | Hung-Cheng Wu,
Tien-Fu Chen,
Hung-Yu Li,
Jinn-Shyan Wang:
Energy Efficient Caching-on-Cache Architectures for Embedded Systems.
J. Inf. Sci. Eng. 19(5): 809-825 (2003) |
15 | EE | Yung-Cheng Ma,
Jih-Ching Chiu,
Tien-Fu Chen,
Chung-Ping Chung:
Variable-size data item placement for load and storage balancing.
Journal of Systems and Software 66(2): 157-166 (2003) |
2002 |
14 | EE | Jian-Liang Kuo,
Tien-Fu Chen:
Dynamic voltage leveling scheduling for real-time embedded systems on low-power variable speed processors.
CASES 2002: 147-155 |
13 | EE | Yung-Cheng Ma,
Tien-Fu Chen,
Chung-Ping Chung:
Posting file partitioning and parallel information retrieval.
Journal of Systems and Software 63(2): 113-127 (2002) |
12 | EE | Tien-Fu Chen,
Yi-Min Hwang:
Decoupling of data and tag arrays for on-chip caches.
Microprocessors and Microsystems 25(9-10): 437-447 (2002) |
2001 |
11 | EE | Chung-Hung Lai,
Tien-Fu Chen:
Compressing inverted files in scalable information systems by binary decision diagram encoding .
SC 2001: 60 |
2000 |
10 | EE | Chi-Min Lin,
Tien-Fu Chen:
Dynamic memory management for real-time embedded Java chips.
RTCSA 2000: 49-56 |
1998 |
9 | EE | Tien-Fu Chen:
Supporting Highly-Speculative Execution via Adaptive Branch Trees.
HPCA 1998: 185-194 |
1996 |
8 | EE | Tien-Fu Chen:
Efficient trace-sampling simulation techniques for cache performance analysis.
Annual Simulation Symposium 1996: 54- |
7 | EE | Tien-Fu Chen:
Techniques for The Efficient Analysis of Cache Performance.
J. Inf. Sci. Eng. 12(4): 483-509 (1996) |
1995 |
6 | EE | Tien-Fu Chen:
An effective programmable prefetch engine for on-chip caches.
MICRO 1995: 237-242 |
5 | | Tien-Fu Chen,
Jean-Loup Baer:
Effective Hardware Based Data Prefetching for High-Performance Processors.
IEEE Trans. Computers 44(5): 609-623 (1995) |
1994 |
4 | | Jean-Loup Baer,
Tien-Fu Chen:
An Evaluation of Hardware and Software Data Prefetching.
Applications in Parallel and Distributed Computing 1994: 257-266 |
3 | | Tien-Fu Chen,
Jean-Loup Baer:
A Performance Study of Software and Hardware Data Prefetching Schemes.
ISCA 1994: 223-232 |
1992 |
2 | | Tien-Fu Chen,
Jean-Loup Baer:
Reducing Memory Latency via Non-blocking and Prefetching Caches.
ASPLOS 1992: 51-61 |
1991 |
1 | EE | Jean-Loup Baer,
Tien-Fu Chen:
An effective on-chip preloading scheme to reduce data access penalty.
SC 1991: 176-186 |