| 2009 |
|---|
| 46 | EE | Chih-Da Chien,
Cheng-An Chien,
Jui-Chin Chu,
Jiun-In Guo,
Ching-Hwa Cheng:
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
| 2007 |
|---|
| 45 | EE | Jui-Chin Chu,
Wei-Chun Ku,
Shu-Hsuan Chou,
Tien-Fu Chen,
Jiun-In Guo:
An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model.
DAC 2007: 652-657 |
| 44 | EE | Chih-Da Chien,
Chih-Wei Wang,
Chiun-Chau Lin,
Tien-Wei Hsieh,
Yuan-Hwa Chu,
Jiun-In Guo:
A Low Latency Memory Controller for Video Coding Systems.
ICME 2007: 1211-1214 |
| 43 | EE | Guo-An Jian,
Jiun-In Guo:
Low Complexity Multi-Standard Video Player for Portable Multimedia Applications.
ICME 2007: 7 |
| 42 | EE | Guo-An Jian,
Chih-Da Chien,
Jiun-In Guo:
A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation.
ISCAS 2007: 1569-1572 |
| 41 | EE | Kuan-Hung Chen,
Yuan-Sun Chu,
Yu-Min Chen,
Jiun-In Guo:
A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique.
ISCAS 2007: 3139-3142 |
| 2006 |
|---|
| 40 | EE | Ching-Lung Su,
Wei-Sen Yang,
Ya-Li Chen,
Yao-Chang Yang,
Ching-Wen Chen,
Jiun-In Guo,
Shau-Yin Tseng:
A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC.
APCCAS 2006: 398-401 |
| 39 | EE | Ching-Lung Su,
Wei-Sen Yang,
Ya-Li Chen,
Yao Li,
Ching-Wen Chen,
Jiun-In Guo,
Shau-Yin Tseng:
Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC.
APCCAS 2006: 578-581 |
| 38 | EE | Ming-Shuan Lee,
Jui-Chin Chu,
Jiun-In Guo:
Predictive Mode Searching Policy for H.264/AVC Intra Prediction.
APCCAS 2006: 764-767 |
| 37 | EE | Jia-Wei Chen,
Chun-Hao Chang,
Chien-Chang Lin,
Yi-Huan Yang,
Jiun-In Guo,
Jinn-Shyan Wang:
A Condition-based Intra Prediction Algorithm for H.264/AVC.
ICME 2006: 1077-1080 |
| 36 | EE | Wei-Chun Ku,
Shu-Hsuan Chou,
Jui-Chin Chu,
Chih-Heng Kang,
Tien-Fu Chen,
Jiun-In Guo:
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications.
ICME 2006: 25-28 |
| 35 | EE | Yao-Chang Yang,
Chien-Chang Lin,
Hsui-Cheng Chang,
Ching-Lung Su,
Jiun-In Guo:
A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing.
ICME 2006: 357-360 |
| 34 | EE | Chih-Da Chien,
Keng-Po Lu,
Yi-Hung Shih,
Jiun-In Guo:
A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications.
ISCAS 2006 |
| 33 | EE | Jia-Wei Chen,
Kuan-Hung Chen,
Jinn-Shyan Wang,
Jiun-In Guo:
A performance-aware IP core design for multimode transform coding using scalable-DA algorithm.
ISCAS 2006 |
| 32 | EE | Jui-Chin Chu,
Chih-Wen Huang,
He-Chun Chen,
Keng-Po Lu,
Ming-Shuan Lee,
Jiun-In Guo,
Tien-Fu Chen:
Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications.
ISCAS 2006 |
| 31 | EE | Kuo-Chuan Chao,
Kuan-Hung Chen,
Yuan-Sun Chu,
Jiun-In Guo:
Low-power mechanism with power block management.
ISCAS 2006 |
| 30 | EE | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang:
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264.
IEEE Trans. Circuits Syst. Video Techn. 16(4): 472-483 (2006) |
| 2005 |
|---|
| 29 | EE | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang:
An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264.
ISCAS (5) 2005: 4517-4520 |
| 28 | EE | Chih-Da Chien,
Ho-Chun Chen,
Lin-Chieh Huang,
Jiun-In Guo:
A low-power motion compensation IP core design for MPEG-1/2/4 video decoding.
ISCAS (5) 2005: 4542-4545 |
| 27 | EE | Hsiu-Cheng Chang,
Chien-Chang Lin,
Jiun-In Guo:
A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding.
ISCAS (6) 2005: 6110-6113 |
| 26 | EE | Kuan-Hung Chen,
Kuo-Chuan Chao,
Jinn-Shyan Wang,
Yuan-Sun Chu,
Jiun-In Guo:
An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design.
ISLPED 2005: 155-160 |
| 25 | EE | Hun-Chen Chen,
Jiun-In Guo,
Tian-Sheuan Chang,
Chein-Wei Jen:
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform.
IEEE Trans. Circuits Syst. Video Techn. 15(3): 445-453 (2005) |
| 24 | EE | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang,
Ching-Wei Yeh,
Jia-Wei Chen:
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms.
IEEE Trans. Circuits Syst. Video Techn. 15(5): 704-715 (2005) |
| 23 | EE | Hun-Chen Chen,
Tian-Sheuan Chang,
Jiun-In Guo,
Chein-Wei Jen:
The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning.
IEICE Transactions 88-C(5): 1061-1069 (2005) |
| 2004 |
|---|
| 22 | | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang,
Ching-Wei Yeh:
A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding.
ICME 2004: 1683-1686 |
| 21 | | Tai-Lun Chang,
Ying-Ming Tsai,
Chih-Da Chien,
Chien-Chang Lin,
Jiun-In Guo:
A high-performance MPEG4 bitstream processing core.
ICME 2004: 467-470 |
| 20 | | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang,
Ching-Wei Yeh,
Tien-Fu Chen:
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms.
ISCAS (2) 2004: 141-144 |
| 19 | | Rei-Chin Ju,
Jia-Wei Chen,
Jiun-In Guo,
Tien-Fu Chen:
A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT.
ISCAS (2) 2004: 769-772 |
| 18 | EE | Chih-Da Chien,
Chien-Chang Lin,
Jiun-In Guo,
Tien-Fu Chen:
A power-aware IP core generator for the one-dimensional discrete Fourier transform.
ISCAS (3) 2004: 637-640 |
| 17 | EE | Jiun-In Guo,
Rei-Chin Ju,
Jia-Wei Chen:
An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization.
IEEE Trans. Circuits Syst. Video Techn. 14(4): 416-428 (2004) |
| 2003 |
|---|
| 16 | EE | Jiun-In Guo,
Jia-Wei Chen,
Han-Chen Chen:
A new 2-D 8/spl times/8 DCT/IDT core design using group distributed arithmetic.
ISCAS (2) 2003: 752-755 |
| 15 | EE | Hun-Chen Chen,
Jiun-In Guo,
Chein-Wei Jen:
A memory efficient realization of cyclic convolution and its application to discrete cosine transform.
ISCAS (4) 2003: 33-36 |
| 14 | EE | Jiun-In Guo,
Chih-Da Chien,
Chien-Chang Lin:
A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining.
ISCAS (5) 2003: 293-296 |
| 13 | EE | Jiun-In Guo,
Jui-Cheng Yen:
An Efficient IDCT Processor Design for HDTV Applications.
VLSI Signal Processing 33(1-2): 147-155 (2003) |
| 2002 |
|---|
| 12 | EE | Hun-Chen Chen,
Jui-Cheng Yen,
Jiun-In Guo:
Design of a New Cryptography System.
IEEE Pacific Rim Conference on Multimedia 2002: 1041-1048 |
| 11 | EE | Hun-Chen Chen,
Jiun-In Guo,
Chein-Wei Jen:
A new group distributed arithmetic design for the one dimensional discrete Fourier transform.
ISCAS (1) 2002: 421-424 |
| 10 | EE | Jui-Cheng Yen,
Jiun-In Guo:
Design of a new signal security system.
ISCAS (4) 2002: 121-124 |
| 9 | EE | Jiun-In Guo,
Chien-Chang Lin:
A new hardware efficient design for the one dimensional discrete Fourier transform.
ISCAS (5) 2002: 549-552 |
| 8 | EE | Jiun-In Guo,
Chien-Chang Lin,
Chih-Da Chien:
A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths.
Journal of Circuits, Systems, and Computers 11(4): 405-428 (2002) |
| 2001 |
|---|
| 7 | EE | Jiun-In Guo:
A low cost 2-D inverse discrete cosine transform design for image compression.
ISCAS (4) 2001: 658-661 |
| 6 | EE | Jiun-In Guo:
A new DA-based array for one dimensional discrete Hartley transform.
ISCAS (4) 2001: 662-665 |
| 5 | | Jiun-In Guo,
Chih-Chen Li:
A generalized architecture for the one-dimensional discrete cosine and sine transforms.
IEEE Trans. Circuits Syst. Video Techn. 11(7): 874-881 (2001) |
| 1998 |
|---|
| 4 | EE | Jui-Cheng Yen,
Jiun-In Guo,
Hun-Chen Chen:
A new k-winners-take-all neural network and its array architecture.
IEEE Transactions on Neural Networks 9(5): 901-912 (1998) |
| 1994 |
|---|
| 3 | | Jiun-In Guo,
Chi-Min Liu,
Chein-Wei Jen:
A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform.
ISCAS 1994: 235-238 |
| 1993 |
|---|
| 2 | | Jiun-In Guo,
Chi-Min Liu,
Chein-Wei Jen:
A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform.
ISCAS 1993: 1571-1574 |
| 1 | | Yu-Sheng Lin,
Jiun-In Guo,
C. Bernard Shung,
Chein-Wei Jen:
A Multi-phase Shared Bus Structure for the Fast Fourier Transform.
ISCAS 1993: 1575-1578 |
