| 2009 |
|---|
| 8 | EE | Xiaoji Ye,
Peng Li:
An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation.
ISQED 2009: 634-640 |
| 2008 |
|---|
| 7 | EE | Wei Dong,
Peng Li,
Xiaoji Ye:
WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines.
DAC 2008: 238-243 |
| 6 | EE | Xiaoji Ye,
Wei Dong,
Peng Li,
Sani R. Nassif:
MAPS: multi-algorithm parallel circuit simulation.
ICCAD 2008: 73-78 |
| 5 | EE | Xiaoji Ye,
Min Zhao,
Rajendran Panda,
Peng Li,
Jiang Hu:
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.
ISQED 2008: 627-632 |
| 2007 |
|---|
| 4 | EE | Xiaoji Ye,
Yaping Zhan,
Peng Li:
Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization.
DAC 2007: 853-858 |
| 3 | EE | Xiaoji Ye,
Peng Li,
Min Zhao,
Rajendran Panda,
Jiang Hu:
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.
ICCAD 2007: 627-631 |
| 2 | EE | Xiaoji Ye,
Frank Liu,
Peng Li:
Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models.
IEEE Trans. VLSI Syst. 15(8): 913-926 (2007) |
| 2006 |
|---|
| 1 | EE | Xiaoji Ye,
Peng Li,
Frank Liu:
Practical variation-aware interconnect delay and slew analysis for statistical timing verification.
ICCAD 2006: 54-59 |
