2009 |
53 | EE | David Bañeres,
Jordi Cortadella,
Michael Kishinevsky:
Timing-driven N-way decomposition.
ACM Great Lakes Symposium on VLSI 2009: 363-368 |
52 | EE | David Bañeres,
Jordi Cortadella,
Michael Kishinevsky:
A Recursive Paradigm to Solve Boolean Relations.
IEEE Trans. Computers 58(4): 512-527 (2009) |
2008 |
51 | EE | Michael Kishinevsky,
Jordi Cortadella:
Time elastic digital systems and Petri Nets.
ACSD 2008: 1-2 |
50 | EE | Josep Carmona,
Jordi Cortadella,
Michael Kishinevsky:
A Region-Based Algorithm for Discovering Petri Nets from Event Logs.
BPM 2008: 358-373 |
49 | EE | Timothy Kam,
Michael Kishinevsky,
Jordi Cortadella,
Marc Galceran Oms:
Correct-by-construction microarchitectural pipelining.
ICCAD 2008: 434-441 |
48 | EE | Steve Haynal,
Timothy Kam,
Michael Kishinevsky,
Emily Shriver,
Xinning Wang:
A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study.
MEMOCODE 2008: 79-88 |
47 | EE | Josep Carmona,
Jordi Cortadella,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Alexandre Yakovlev:
A Symbolic Algorithm for the Synthesis of Bounded Petri Nets.
Petri Nets 2008: 92-111 |
46 | EE | Jordi Cortadella,
Michael Kishinevsky,
Dmitry Bufistov,
Josep Carmona,
Jorge Júlvez:
Elasticity and Petri Nets.
T. Petri Nets and Other Models of Concurrency 1: 221-249 (2008) |
2007 |
45 | EE | Jordi Cortadella,
Michael Kishinevsky:
Synchronous Elastic Circuits with Early Evaluation and Token Counterflow.
DAC 2007: 416-419 |
44 | EE | David Bañeres,
Jordi Cortadella,
Michael Kishinevsky:
Layout-aware gate duplication and buffer insertion.
DATE 2007: 1367-1372 |
43 | EE | Dmitry Bufistov,
Jordi Cortadella,
Michael Kishinevsky,
Sachin S. Sapatnekar:
A general model for performance optimization of sequential systems.
ICCAD 2007: 362-369 |
42 | EE | Michael Kishinevsky,
Sandeep K. Shukla,
Ken S. Stevens:
Guest Editors' Introduction: GALS Design and Validation.
IEEE Design & Test of Computers 24(5): 414-416 (2007) |
2006 |
41 | EE | David Bañeres,
Jordi Cortadella,
Michael Kishinevsky:
Dominator-based partitioning for delay optimization.
ACM Great Lakes Symposium on VLSI 2006: 67-72 |
40 | EE | Michael Kishinevsky,
Jordi Cortadella,
Bill Grundmann,
Sava Krstic,
John O'Leary:
Synchronous Elastic Circuits.
CSR 2006: 3-5 |
39 | EE | Jordi Cortadella,
Michael Kishinevsky,
Bill Grundmann:
Synthesis of synchronous elastic architectures.
DAC 2006: 657-662 |
38 | EE | Sava Krstic,
Jordi Cortadella,
Michael Kishinevsky,
John O'Leary:
Synchronous Elastic Networks.
FMCAD 2006: 19-30 |
37 | EE | Jorge Júlvez,
Jordi Cortadella,
Michael Kishinevsky:
Performance analysis of concurrent systems with early evaluation.
ICCAD 2006: 448-455 |
2004 |
36 | EE | David Bañeres,
Jordi Cortadella,
Michael Kishinevsky:
A recursive paradigm to solve Boolean relations.
DAC 2004: 416-421 |
35 | EE | Laurent Arditi,
Gérard Berry,
Michael Kishinevsky:
Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs.
FMCAD 2004: 128-143 |
2003 |
34 | EE | Gérard Berry,
Michael Kishinevsky,
Satnam Singh:
System Level Design and Verification Using a Synchronous Language.
ICCAD 2003: 433-440 |
2002 |
33 | EE | Sumit Gupta,
Nick Savoiu,
Nikil D. Dutt,
Rajesh K. Gupta,
Alexandru Nicolau,
Timothy Kam,
Michael Kishinevsky,
Shai Rotem:
Coordinated transformations for high-level synthesis of high performance microprocessor blocks.
DAC 2002: 898-903 |
32 | EE | Jordi Cortadella,
Michael Kishinevsky,
Steven M. Burns,
Alex Kondratyev,
Luciano Lavagno,
Ken S. Stevens,
Alexander Taubin,
Alexandre Yakovlev:
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 109-130 (2002) |
2000 |
31 | EE | Jordi Cortadella,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Alexandre Yakovlev:
Hardware and Petri Nets: Application to Asynchronous Circuit Design.
ICATPN 2000: 1-15 |
1999 |
30 | EE | Alex Kondratyev,
Jordi Cortadella,
Michael Kishinevsky,
Luciano Lavagno,
Alexandre Yakovlev:
Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems.
DAC 1999: 110-115 |
29 | EE | Ken S. Stevens,
Shai Rotem,
Steven M. Burns,
Jordi Cortadella,
Ran Ginosar,
Michael Kishinevsky,
Marly Roncken:
CAD Directions for High Performance Asynchronous Circuits.
DAC 1999: 116-121 |
28 | EE | Jordi Cortadella,
Michael Kishinevsky,
Steven M. Burns,
Ken S. Stevens:
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions.
ICCAD 1999: 324-331 |
27 | EE | Jordi Cortadella,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Enric Pastor,
Alexandre Yakovlev:
Decomposition and technology mapping of speed-independent circuits using Boolean relations.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1221-1236 (1999) |
1998 |
26 | EE | Alex Kondratyev,
Jordi Cortadella,
Michael Kishinevsky,
Luciano Lavagno,
Alexander Taubin,
Alexandre Yakovlev:
Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings.
ACSD 1998: 152- |
25 | EE | Michael Kishinevsky,
Jordi Cortadella,
Alex Kondratyev:
Asynchronous Interface Specification, Analysis and Synthesis.
DAC 1998: 2-7 |
24 | EE | Jordi Cortadella,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Alexander Taubin,
Alexandre Yakovlev:
Lazy transition systems: application to timing optimization of asynchronous circuits.
ICCAD 1998: 324-331 |
23 | | Alex Kondratyev,
Michael Kishinevsky,
Alexander Taubin,
Sergei Ten:
Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings.
Formal Methods in System Design 12(1): 5-38 (1998) |
22 | | Jordi Cortadella,
Michael Kishinevsky,
Luciano Lavagno,
Alexandre Yakovlev:
Deriving Petri Nets for Finite Transition Systems.
IEEE Trans. Computers 47(8): 859-882 (1998) |
21 | EE | Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Alexander Saldanha,
Alexander Taubin:
Partial-scan delay fault testing of asynchronous circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1184-1199 (1998) |
20 | EE | Alex Kondratyev,
Michael Kishinevsky,
Alexandre Yakovlev:
Hazard-free implementation of speed-independent circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 749-771 (1998) |
19 | EE | Alex Kondratyev,
Michael Kishinevsky,
Alexander Taubin,
Jordi Cortadella,
Luciano Lavagno:
The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems.
Journal of Circuits, Systems, and Computers 8(1): 67-118 (1998) |
1997 |
18 | EE | Alex Kondratyev,
Michael Kishinevsky,
Jordi Cortadella,
Luciano Lavagno,
Alexandre Yakovlev:
Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis.
ASYNC 1997: 240-253 |
17 | EE | Jordi Cortadella,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Alexandre Yakovlev:
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis.
ED&TC 1997: 98-105 |
16 | | Michael Kishinevsky,
Jordi Cortadella,
Alex Kondratyev,
Luciano Lavagno,
Alexander Taubin,
Alexandre Yakovlev:
Coupling Asynchrony and Interrupts: Place Chart Nets.
ICATPN 1997: 328-347 |
15 | EE | Jordi Cortadella,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Enric Pastor,
Alexandre Yakovlev:
Decomposition and technology mapping of speed-independent circuits using Boolean relations.
ICCAD 1997: 220-227 |
14 | EE | Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Alexander Saldanha,
Alexander Taubin:
Partial scan delay fault testing of asynchronous circuits.
ICCAD 1997: 728-735 |
13 | EE | Jordi Cortadella,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Alexandre Yakovlev:
A region-based theory for state assignment in speed-independent circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 793-812 (1997) |
1996 |
12 | | Alex Kondratyev,
Michael Kishinevsky,
Alexander Taubin,
Sergei Ten:
A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings.
Application and Theory of Petri Nets 1996: 346-365 |
11 | EE | Jordi Cortadella,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Alexandre Yakovlev:
Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis.
DAC 1996: 63-66 |
10 | | Alexandre Yakovlev,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno,
Marta Pietkiewicz-Koutny:
On the Models for Asynchronous Circuit Behaviour with OR Causality.
Formal Methods in System Design 9(3): 189-233 (1996) |
1995 |
9 | EE | Alex Kondratyev,
Michael Kishinevsky,
Alexandre Yakovlev:
On hazard-free implementation of speed-independent circuits.
ASP-DAC 1995 |
8 | EE | Jordi Cortadella,
Michael Kishinevsky,
Luciano Lavagno,
Alexandre Yakovlev:
Synthesizing Petri nets from state-based models.
ICCAD 1995: 164-171 |
1994 |
7 | | Alexandre Yakovlev,
Michael Kishinevsky,
Alex Kondratyev,
Luciano Lavagno:
OR Causality: Modelling and Hardware Implementation.
Application and Theory of Petri Nets 1994: 568-587 |
6 | EE | Alex Kondratyev,
Michael Kishinevsky,
Bill Lin,
Peter Vanbekbergen,
Alexandre Yakovlev:
Basic Gate Implementation of Speed-Independent Circuits.
DAC 1994: 56-62 |
5 | EE | Christian D. Nielsen,
Michael Kishinevsky:
Performance Analysis Based on Timing Simulation.
DAC 1994: 70-76 |
4 | EE | Luciano Lavagno,
Antonio Lioy,
Michael Kishinevsky:
Testing redundant asynchronous circuits by variable phase splitting.
EURO-DAC 1994: 328-333 |
3 | | Michael Kishinevsky,
Alex Kondratyev,
Alexander Taubin,
Victor Varshavsky:
Analysis and Identification of Speed-Independent Circuits on an Event Model.
Formal Methods in System Design 4(1): 33-75 (1994) |
2 | EE | Michael Kishinevsky,
Alex Kondratyev,
Alexander Taubin:
Specification and analysis of self-timed circuits.
VLSI Signal Processing 7(1-2): 117-135 (1994) |
1992 |
1 | | Michael Kishinevsky,
Alex Kondratyev,
Alexander Taubin,
Victor Varshavsky:
Analysis and Identification of Self-Timed Circuits.
Designing Correct Circuits 1992: 275-287 |