| 2008 |
|---|
| 4 | EE | Saurabh Sinha,
Asha Balijepalli,
Yu Cao:
A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design.
ISQED 2008: 502-507 |
| 2007 |
|---|
| 3 | EE | Ritu Singhal,
Asha Balijepalli,
Anupama Subramaniam,
Frank Liu,
Sani R. Nassif,
Yu Cao:
Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.
DAC 2007: 823-828 |
| 2 | EE | Asha Balijepalli,
Saurabh Sinha,
Yu Cao:
Compact modeling of carbon nanotube transistor for early stage process-design exploration.
ISLPED 2007: 2-7 |
| 1 | EE | Asha Balijepalli,
Joseph Ervin,
Yu Cao,
Trevor Thornton:
Compact Modeling of a PD SOI MESFET for Wide Temperature Designs.
ISQED 2007: 133-138 |
