ITC 2001:
Baltimore, MD, USA
Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001.
IEEE Computer Society 2001, ISBN 0-7803-7169-0 BibTeX
Session 2: IEE 1149 - Beyond DC Testing At Board Test
Session 3: Bist Medley
Session 4: How Can We Improve Iddq Testing for DSM/VDSM?
Session 5: Practical Experience With SOC Testing
- Patrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre:
A building block BIST methodology for SOC designs: a case study.
111-120 BibTeX
- Bart Vermeulen, Steven Oostdijk, Frank Bouwman:
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip.
121-130 BibTeX
- Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay:
CTL the language for describing core-based test.
131-139 BibTeX
Session 6: Some Thorny Problems For Ate Software
Session 7: Lecture Series: Test and Repair Of Large Embedded Drams
- Roderick McConnell, Rochit Rajsuman, Eric A. Nelson, Jeffrey Dreibelbis:
Test and repair of large embedded DRAMs. I.
163-172 BibTeX
- Eric A. Nelson, Jeffrey Dreibelbis, Roderick McConnell:
Test and repair of large embedded DRAMs. 2.
173-181 BibTeX
- Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada:
Test cost reduction by at-speed BISR for embedded DRAMs.
182-187 BibTeX
Session 8: DFT Innovations
Session 9: On-line Test
Session 10: Novel Techniques For Fault Diagnosis
- John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly:
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring.
258-267 BibTeX
- Ruifeng Guo, Srikanth Venkataraman:
A technique for fault diagnosis of defects in scan chains.
268-277 BibTeX
- David B. Lavo, Tracy Larrabee:
Making cause-effect cost effective: low-resolution fault dictionaries.
278-286 BibTeX
- Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski:
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm.
287-296 BibTeX
Session 11: Testing Above GigaHertz
- Bernd Laquai, Yi Cai:
Testing gigabit multilane SerDes interfaces with passive jitter injection filters.
297-304 BibTeX
- Amir Attarha, Mehrdad Nourani:
Testing interconnects for noise and skew in gigahertz SoCs.
305-314 BibTeX
- Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang:
A built-in timing parametric measurement unit.
315-322 BibTeX
- Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida:
Testing clock distribution circuits using an analytic signal method.
323-331 BibTeX
Session 12: Test Methods For High-density Modules
Session 13: High-quality Test
Session 14: New IDDX and Energy Test Techniques
Session 15: ATE Hardware: Improving Your Test Results
Session 16: Advanced Microprocessor Test Methodologies
- Ken Tumin, Carmen Vargas, Ross Patterson, Chris Nappi:
Scan vs. functional testing - a comparative effectiveness study on Motorola's MMC2107TM.
443-450 BibTeX
- Don Douglas Josephson, Steve Poehhnan, Vincent Govan:
Debug methodology for the McKinley processor.
451-460 BibTeX
- Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich:
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.
461-469 BibTeX
Session 17: Lecture Series - Solving Board Test and In-System Problems
Session 18: Mixed-Signal Test Techniques
Session 19: Advanced Techniques for Embedded Core Testing
Session 20: Test Generation for Crosstalk Faults
Session 21: Microprocessor Testing
Session 22: Standards and Techniques - Board Test Development
Session 23: Delay Test
Session 24: Ideas for Low-Power Scan Operation
Session 25: Uncovering and Understanding Why Circuits Fail
Session 26: ATE HW: Conquering Those Stubborn Test Problems
Session 27: Advances in Scan Testing
- Rohit Kapur, Thomas W. Williams:
Tester retargetable patterns.
721-727 BibTeX
- Yu Huang, Chien-Chung Tsai, Neelanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy:
On RTL scan design.
728-737 BibTeX
- Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier:
Enhanced reduced pin-count test for full-scan design.
738-747 BibTeX
- Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Könemann, Andrej Ferko:
OPMISR: the foundation for compressed ATPG vectors.
748-757 BibTeX
Session 28: Memory Testing
- Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
March-based RAM diagnosis algorithms for stuck-at and coupling faults.
758-767 BibTeX
- Jörg E. Vollrath, Randall Rooney:
Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment.
768-775 BibTeX
- Herold Pilo, R. Dean Adams, Robert E. Busch, Eric A. Nelson, Geoerge E. Rudgers:
Bitline contacts in high density SRAMs: design for testability and stressability.
776-782 BibTeX
- Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter:
Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs.
783-792 BibTeX
Session 29: Increasing Design Validation Coverage
Session 30: PLL AND Jitter Testing
Session 31: New Ideas for BIST TPG
Session 32: Test Automation; Improbing IC Test Efficiency
Session 33: FPGA Testing
Session 34: RF Testing
Session 35: Embedded Memories Test and Repair
- Peter Jakobsen, Jeffrey Dreibelbis, Gary Pomichter, Darren Anand, John E. Barth Jr., Michael R. Nelms, Jeffrey Leach, George M. Belansek:
Embedded DRAM built in self test and methodology for test insertion.
975-984 BibTeX
- Yuejian Wu, Liviu Calin:
Shadow write and read for at-speed BIST of TDM SRAMs.
985-994 BibTeX
- Volker Schöber, Steffen Paul, Olivier Picot:
Memory built-in self-repair using redundant words.
995-1001 BibTeX
Session 36: Lecture Series - Logic BIST Case Studies
Session 37: Advanced Methods in Embedded Core Test
Session 38: How Could We Model and Test VDSM Defects
- Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand:
Boolean and current detection of MOS transistor with gate oxide short.
1039-1048 BibTeX
- Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey:
Testing for resistive opens and stuck opens.
1049-1058 BibTeX
- Yasuo Sato, Msaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto:
An evaluation of defect-oriented test: WELL-controlled low voltage test.
1059-1067 BibTeX
Session 39: Practical Test Generation Techniques
Session 40: Delving into Factors Affecting Manufacturing Cost
Session 41: ATE Hardware: From GigaHertz to TeraHertz
ITC 2000 Best Paper
Copyright © Sat May 16 23:26:44 2009
by Michael Ley (ley@uni-trier.de)
