2006 |
14 | EE | Sagar S. Sabade,
D. M. H. Walker:
Estimation of fault-free leakage current using wafer-level spatial information.
IEEE Trans. VLSI Syst. 14(1): 91-94 (2006) |
2005 |
13 | EE | Sagar S. Sabade,
Duncan M. Walker:
IC Outlier Identification Using Multiple Test Metrics.
IEEE Design & Test of Computers 22(6): 586-595 (2005) |
2004 |
12 | EE | Sagar S. Sabade,
D. M. H. Walker:
Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests.
VLSI Design 2004: 889-894 |
11 | EE | Sagar S. Sabade,
D. M. H. Walker:
On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set.
VTS 2004: 65-72 |
10 | EE | Sagar S. Sabade,
D. M. H. Walker:
IDDX-based test methods: A survey.
ACM Trans. Design Autom. Electr. Syst. 9(2): 159-198 (2004) |
9 | EE | Sagar S. Sabade,
D. M. H. Walker:
IDDQ data analysis using neighbor current ratios.
Journal of Systems Architecture 50(5): 287-294 (2004) |
2003 |
8 | EE | Sagar S. Sabade,
D. M. H. Walker:
CROWNE: Current Ratio Outliers with Neighbor Estimator.
DFT 2003: 132-139 |
7 | EE | Sagar S. Sabade,
D. M. H. Walker:
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification.
VLSI Design 2003: 361- |
6 | EE | Sagar S. Sabade,
D. M. H. Walker:
Use of Multiple IDDQ Test Metrics for Outlier Identification.
VTS 2003: 31-38 |
2002 |
5 | EE | Sagar S. Sabade,
D. M. H. Walker:
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis.
DFT 2002: 381-389 |
4 | EE | Sagar S. Sabade,
D. M. H. Walker:
Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting.
VLSI Design 2002: 755-760 |
3 | EE | Sagar S. Sabade,
D. M. H. Walker:
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction.
VTS 2002: 81-86 |
2 | EE | Sagar S. Sabade,
D. M. H. Walker:
IDDQ Test: Will It Survive the DSM Challenge?
IEEE Design & Test of Computers 19(5): 8-16 (2002) |
2001 |
1 | | Sagar S. Sabade,
D. M. H. Walker:
Improved wafer-level spatial analysis for I_DDQ limit setting.
ITC 2001: 82-91 |