| 2005 |
|---|
| 7 | EE | Yong Chang Kim,
Vishwani D. Agrawal,
Kewal K. Saluja:
Combinational automatic test pattern generation for acyclic sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 948-956 (2005) |
| 2003 |
|---|
| 6 | EE | Vishwani D. Agrawal,
Dong Hyun Baik,
Yong Chang Kim,
Kewal K. Saluja:
Exclusive Test and its Applications to Fault Diagnosis.
VLSI Design 2003: 143-148 |
| 2002 |
|---|
| 5 | EE | Yong Chang Kim,
Vishwani D. Agrawal,
Kewal K. Saluja:
Multiple Faults: Modeling, Simulation and Test.
VLSI Design 2002: 592-597 |
| 2001 |
|---|
| 4 | | Yong Chang Kim,
Vishwani D. Agrawal,
Kewal K. Saluja:
Combinational test generation for various classes of acyclic sequential circuits.
ITC 2001: 1078-1087 |
| 3 | EE | Yong Chang Kim,
Kewal K. Saluja,
Vishwani D. Agrawal:
Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.
VLSI Design 2001: 143-148 |
| 1999 |
|---|
| 2 | EE | Yong Chang Kim,
Kewal K. Saluja,
Vishwani D. Agrawal:
A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability.
Great Lakes Symposium on VLSI 1999: 300- |
| 1998 |
|---|
| 1 | EE | Yong Chang Kim,
Kewal K. Saluja:
Sequential test generators: past, present and future.
Integration 26(1-2): 41-54 (1998) |
