Elizabeth M. Rudnick

2004
56	EE	Dirk Niggemeyer, Elizabeth M. Rudnick: Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing. IEEE Trans. Computers 53(9): 1134-1146 (2004)
2003
55	EE	Dirk Niggemeyer, Elizabeth M. Rudnick: A data acquisition methodology for on-chip repair of embedded memories. ACM Trans. Design Autom. Electr. Syst. 8(4): 560-576 (2003)
2002
54	EE	Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick: Low-cost sequential ATPG with clock-control DFT. DAC 2002: 243-248
53		Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick: Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm. GECCO 2002: 1275
52	EE	Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick: A Genetic Testing Framework for Digital Integrated Circuits. ICTAI 2002: 521-526
2001
51	EE	Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir: Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. IOLTW 2001: 65-
50		Jongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici: At-speed logic BIST using a frozen clock testing strategy. ITC 2001: 64-71
49	EE	Dirk Niggemeyer, Elizabeth M. Rudnick: Automatic Generation of Diagnostic March Tests. VTS 2001: 299-305
48	EE	Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty: Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ACM Trans. Design Autom. Electr. Syst. 6(4): 471-489 (2001)
47	EE	Franco Fummi, Marco Boschini, Xiaoming Yu, Elizabeth M. Rudnick: Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach. J. Electronic Testing 17(3-4): 321-330 (2001)
2000
46	EE	Timothy J. Bergfeld, Dirk Niggemeyer, Elizabeth M. Rudnick: Diagnostic Testing of Embedded Memories Using BIST. DATE 2000: 305-
45		Xiaoming Yu, Jue Wu, Elizabeth M. Rudnick: Diagnostic test generation for sequential circuits. ITC 2000: 225-234
44	EE	Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Redeker: Diagnostic Testing of Embedded Memories Based on Output Tracing. MTDT 2000: 113-118
43	EE	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Dynamic state traversal for sequential circuit test generation. ACM Trans. Design Autom. Electr. Syst. 5(3): 548-565 (2000)
42	EE	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Peak power estimation of VLSI circuits: new peak power measures. IEEE Trans. VLSI Syst. 8(4): 435-439 (2000)
41	EE	Jue Wu, Elizabeth M. Rudnick: Bridge fault diagnosis using stuck-at fault simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 489-495 (2000)
40	EE	Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick: A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. J. Electronic Testing 16(1-2): 13-27 (2000)
39	EE	Elizabeth M. Rudnick, Miron Abramovici: Compact Test Generation Using a Frozen Clock Testing Strategy. J. Inf. Sci. Eng. 16(5): 703-717 (2000)
1999
38	EE	Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici: FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. DATE 1999: 747-
37	EE	Jue Wu, Gary S. Greenstein, Elizabeth M. Rudnick: A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis. DATE 1999: 780-781
36	EE	Jue Wu, Elizabeth M. Rudnick: A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults. VLSI Design 1999: 498-505
35		Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. IEEE Trans. Computers 48(3): 311-322 (1999)
34		Elizabeth M. Rudnick, Janak H. Patel: Efficient Techniques for Dynamic Test Sequence Compaction. IEEE Trans. Computers 48(3): 323-330 (1999)
1998
33	EE	Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda: Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. DATE 1998: 570-576
32	EE	Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel: Partial Scan Selection Based on Dynamic Reachability and Observability Information. VLSI Design 1998: 174-180
31	EE	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 239-254 (1998)
1997
30	EE	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Sequential circuit test generation using dynamic state traversal. ED&TC 1997: 22-28
29	EE	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Effects of delay models on peak power estimation of VLSI sequential circuits. ICCAD 1997: 45-51
28	EE	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: K2: an estimator for peak sustainable power of VLSI circuits. ISLPED 1997: 178-183
27		Elizabeth M. Rudnick, Janak H. Patel: Putting the Squeeze on Test Sequences. ITC 1997: 723-732
26	EE	Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee: Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. VLSI Design 1997: 475-481
25	EE	Elizabeth M. Rudnick, Janak H. Patel: Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. VLSI Design 1997: 495-503
24	EE	Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel: Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. VLSI Design 1997: 542-544
23	EE	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. VTS 1997: 188-195
22	EE	Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee: SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. VTS 1997: 274-281
21	EE	Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel: Static logic implication with application to redundancy identification. VTS 1997: 288-295
20	EE	Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel: Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. Workshop on Parallel and Distributed Simulation 1997: 30-37
19	EE	Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann: A genetic algorithm framework for test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1034-1044 (1997)
1996
18	EE	Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel: Enhancing high-level control-flow for improved testability. ICCAD 1996: 322-328
17	EE	Elizabeth M. Rudnick, Janak H. Patel: Simulation-based techniques for dynamic test sequence compaction. ICCAD 1996: 67-73
16	EE	Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel: Testability Insertion in Behavioral Descriptions. ISSS 1996: 139-144
15		Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz: On Potential Fault Detection in Sequential Circuits. ITC 1996: 142-149
14	EE	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Automatic test generation using genetically-engineered distinguishing sequences. VTS 1996: 216-223
13	EE	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel: Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. VTS 1996: 456-462
12		Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi: A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. IEEE Trans. Computers 45(11): 1248-1256 (1996)
1995
11	EE	Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel: Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. DAC 1995: 133-138
10	EE	Elizabeth M. Rudnick, Janak H. Patel: Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. DAC 1995: 183-188
9	EE	Elizabeth M. Rudnick, Janak H. Patel: A genetic approach to test application time reduction for full scan and partial scan circuits. VLSI Design 1995: 288-293
8	EE	Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel: Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. VLSI Syst. 3(2): 333-338 (1995)
1994
7	EE	Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann: Sequential Circuit Test Generation in a Genetic Algorithm Framework. DAC 1994: 698-704
6		Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel: Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. EDAC-ETC-EUROASIC 1994: 40-45
5	EE	Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel: An observability enhancement approach for improved testability and at-speed test. IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1051-1056 (1994)
1993
4	EE	Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel: Non-Scan Design-for-Testability Techniques for Sequential Circuits. DAC 1993: 236-241
3		Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer: A Fast and Accurate Gate-Level Transient Fault Simulation Environment. FTCS 1993: 310-319
1992
2		Elizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel: Diagnostic Fault Simulation of Sequential Circuits. ITC 1992: 178-186
1991
1		Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel: Methods for Reducing Events in Sequential Circuit Fault Simulation. ICCAD 1991: 546-549

Coauthor Index

1	Magdy S. Abadir	[51]
2	Miron Abramovici	[38] [39] [50] [54]
3	Prithviraj Banerjee (Prith Banerjee)	[4] [8] [20] [22] [26]
4	Timothy J. Bergfeld	[46]
5	Marco Boschini	[47]
6	Mrinal Bose	[51]
7	Hungse Cha	[3] [12]
8	Sreejit Chakravarty	[11] [48]
9	Ta-Chung Chang	[40]
10	Vivek Chickermane	[4] [5] [8]
11	Gwan S. Choi (Gwan Choi)	[3] [12]
12	Fulvio Corno	[33]
13	Akilah Ellis	[33]
14	Alessandro Fin	[52] [53]
15	W. Kent Fuchs	[2] [11] [48]
16	Franco Fummi	[47] [52] [53]
17	Charles R. Graham	[24]
18	Gary S. Greenstein	[7] [19] [37]
19	Ibrahim N. Hajj	[13]
20	Ismed Hartanto	[11] [48]
21	John G. Holm	[6]
22	Michael S. Hsiao	[14] [23] [26] [28] [29] [30] [31] [32] [35] [42] [43]
23	Frank F. Hsu	[16] [18]
24	Vikram Iyengar	[40]
25	Ravishankar K. Iyer (Ravi K. Iyer)	[3] [12]
26	Dilip Krishnaswamy	[20] [22] [26]
27	Terry Lee	[13]
28	Matthew C. Merten	[38]
29	Thomas M. Niermann	[1] [7] [19]
30	Dirk Niggemeyer	[44] [46] [49] [55] [56]
31	Janak H. Patel	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [34] [35] [42] [43] [48]
32	Irith Pomeranz	[15]
33	Paolo Prinetto	[33]
34	Michael Redeker	[44]
35	Matteo Sonza Reorda	[33]
36	Daniel G. Saab	[6]
37	Yanti Santoso	[38]
38	Gurjeet S. Saund	[32]
39	Vikram Saxena	[26]
40	Jongshin Shin	[50]
41	Srikanth Venkataraman	[11] [48]
42	Roberto Vietti	[33]
43	Jue Wu	[36] [37] [41] [45]
44	Xiaoming Yu	[45] [47] [50] [52] [53] [54]
45	Jian-Kun Zhao	[21]

Colors in the list of coauthors