2007 |
12 | EE | Xiaoming Yu,
Yue Liu,
Hongbo Xu:
Density Analysis of Winnowing on Non-uniform Distributions.
APWeb/WAIM 2007: 586-593 |
2006 |
11 | EE | Bharath Seshadri,
Xiaoming Yu,
Srikanth Venkataraman:
Accelerating Diagnostic Fault Simulation Using Z-diagnosis and Concurrent Equivalence Identification.
VTS 2006: 380-385 |
2005 |
10 | EE | Xiaoming Yu,
Miron Abramovici:
Sequential circuit ATPG using combinational algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1294-1310 (2005) |
2003 |
9 | EE | Xiaoming Yu,
Enamul Amyeen,
Srikanth Venkataraman,
Ruifeng Guo,
Irith Pomeranz:
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation.
VTS 2003: 351-358 |
8 | EE | Xiaoming Yu,
Shenghua Zhang,
Erwin Johnson:
A discrete post-processing method for structural optimization.
Eng. Comput. (Lond.) 19(2-3): 213-220 (2003) |
2002 |
7 | EE | Miron Abramovici,
Xiaoming Yu,
Elizabeth M. Rudnick:
Low-cost sequential ATPG with clock-control DFT.
DAC 2002: 243-248 |
6 | | Xiaoming Yu,
Alessandro Fin,
Franco Fummi,
Elizabeth M. Rudnick:
Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm.
GECCO 2002: 1275 |
5 | EE | Xiaoming Yu,
Alessandro Fin,
Franco Fummi,
Elizabeth M. Rudnick:
A Genetic Testing Framework for Digital Integrated Circuits.
ICTAI 2002: 521-526 |
2001 |
4 | | Jongshin Shin,
Xiaoming Yu,
Elizabeth M. Rudnick,
Miron Abramovici:
At-speed logic BIST using a frozen clock testing strategy.
ITC 2001: 64-71 |
3 | EE | Franco Fummi,
Marco Boschini,
Xiaoming Yu,
Elizabeth M. Rudnick:
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach.
J. Electronic Testing 17(3-4): 321-330 (2001) |
2000 |
2 | | Xiaoming Yu,
Jue Wu,
Elizabeth M. Rudnick:
Diagnostic test generation for sequential circuits.
ITC 2000: 225-234 |
1997 |
1 | EE | Xiaoming Yu,
Yinghua Min:
Design of delay-verifiable combinational logic by adding extra inputs.
Asian Test Symposium 1997: 332- |