dblp.uni-trier.dewww.uni-trier.de

Yi-Min Jiang

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
18EEKaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan: Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs. JCP 3(3): 6-13 (2008)
2007
17EEKaijian Shi, Zhian Lin, Yi-Min Jiang: A Power Network Synthesis Method for Industrial Power Gating Designs. ISQED 2007: 362-367
2003
16EEJing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng: Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 756-769 (2003)
2001
15EEYi-Min Jiang, Han Young Koh, Kwang-Ting Cheng: HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. ISQED 2001: 307-312
14 Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng: Delay testing considering crosstalk-induced effects. ITC 2001: 558-567
13EEYi-Min Jiang, Kwang-Ting Cheng: Vector generation for power supply noise estimation and verification of deep submicron designs. IEEE Trans. VLSI Syst. 9(2): 329-340 (2001)
12EEAngela Krstic, Yi-Min Jiang, Kwang-Ting Cheng: Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 416-425 (2001)
2000
11 Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng: Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. ICCAD 2000: 493-496
10EEYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng: Dynamic Timing Analysis Considering Power Supply Noise Effects. ISQED 2000: 137-144
9EEYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng: Estimation for maximum instantaneous current through supply lines for CMOS circuits. IEEE Trans. VLSI Syst. 8(1): 61-73 (2000)
1999
8EEYi-Min Jiang, Kwang-Ting Cheng: Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. DAC 1999: 760-765
7EEYi-Min Jiang, Tak K. Young, Kwang-Ting Cheng: VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs. ISLPED 1999: 156-161
6 Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng: Delay testing considering power supply noise effects. ITC 1999: 181-190
1998
5 Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho: A Hybrid Power Model for RTL Power Estimation. ASP-DAC 1998: 551-556
4EEYi-Min Jiang, Kwang-Ting Cheng: Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits. DATE 1998: 698-
3EEYi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng: Estimation of maximum power supply noise for deep sub-micron designs. ISLPED 1998: 233-238
1997
2EEYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska: Post-Layout Logic Restructuring for Performance Optimization. DAC 1997: 662-665
1994
1EEYi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin: Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 137-149 (1994)

Coauthor Index

1Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
2An-Chang Deng [3]
3ChingYen Ho [5]
4Shi-Yu Huang [5]
5TingTing Hwang [1]
6Han Young Koh [15]
7Angela Krstic [2] [6] [9] [10] [11] [12] [14] [16]
8Tsing-Fa Lee [1]
9Youn-Long Lin [1]
10Zhian Lin [17] [18]
11Jing-Jia Liou [11] [14] [16]
12Malgorzata Marek-Sadowska [2]
13Kaijian Shi [17] [18]
14Deborah C. Wang [5]
15Tak K. Young [7]
16Lin Yuan [18]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)