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Kuen-Jong Lee

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2008
43EETai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee: A hybrid self-testing methodology of processor cores. ISCAS 2008: 3378-3381
42EETai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee: A hybrid software-based self-testing methodology for embedded processor. SAC 2008: 1528-1534
41EETong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: An Error Rate Based Test Methodology to Support Error-Tolerance. IEEE Transactions on Reliability 57(1): 204-214 (2008)
2007
40EETong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: Reduction of detected acceptable faults for yield improvement via error-tolerance. DATE 2007: 1599-1604
2006
39EETong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer: An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. VTS 2006: 130-135
2005
38EEKuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong: An embedded processor based SOC test platform. ISCAS (3) 2005: 2983-2986
2004
37EEKuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho: Test Power Reduction with Multiple Capture Orders. Asian Test Symposium 2004: 26-31
36EEChih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang: A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. Asian Test Symposium 2004: 296-301
2003
35EEKuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng: A Sigma-Delta Modulation Based BIST Scheme for A/D Converters. Asian Test Symposium 2003: 124-129
34EEJih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee: Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 363-370 (2003)
2002
33EEKuen-Jong Lee, Jih-Jeen Chen: Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. Asian Test Symposium 2002: 338-
32EEKuen-Jong Lee, Chau-chin Su: Guest Editorial. J. Electronic Testing 18(1): 15-16 (2002)
31EEWei-Lun Wang, Kuen-Jong Lee: An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. J. Electronic Testing 18(1): 43-53 (2002)
30EEKuen-Jong Lee, Tsung-Chu Huang: An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. J. Electronic Testing 18(6): 627-636 (2002)
2001
29EETsung-Chu Huang, Kuen-Jong Lee: A Low-Power LFSR Architecture. Asian Test Symposium 2001: 470
28 Tsung-Chu Huang, Kuen-Jong Lee: A token scan architecture for low power testing. ITC 2001: 660-669
27EEWei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang: An on-chip march pattern generator for testing embedded memory cores. IEEE Trans. VLSI Syst. 9(5): 730-735 (2001)
26EEYun-Che Wen, Kuen-Jong Lee: Analysis and generation of control and observation structures foranalog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 165-171 (2001)
25EETsung-Chu Huang, Kuen-Jong Lee: Reduction of power consumption in scan-based circuits during testapplication by an input control technique. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 911-917 (2001)
2000
24EEKuen-Jong Lee, Cheng-I. Huang: A hierarchical test control architecture for core based design. Asian Test Symposium 2000: 248-253
23EEWei-Lun Wang, Kuen-Jong Lee: Accelerated test pattern generators for mixed-mode BIST environments. Asian Test Symposium 2000: 368-373
22EEKuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen: Peak-power reduction for multiple-scan circuits during test application. Asian Test Symposium 2000: 453-458
21EEYun-Che Wen, Kuen-Jong Lee: An on Chip ADC Test Structure. DATE 2000: 221-225
1999
20EETsung-Chu Huang, Kuen-Jong Lee: An Input Control Technique for Power Reduction in Scan Circuits During Test Application. Asian Test Symposium 1999: 315-320
19EEKuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang: BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. ACM Trans. Design Autom. Electr. Syst. 4(2): 194-218 (1999)
18EEKuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang: Broadcasting test patterns to multiple circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1793-1802 (1999)
1998
17EEKuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh: On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation. Asian Test Symposium 1998: 113-118
16EEKuen-Jong Lee, Jih-Jeen Chen, Cheng-Hua Huang: Using a single input to support multiple scan chains. ICCAD 1998: 74-78
15EEJing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu: A graph representation for programmable logic arrays to facilitate testing and logic design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1030-1043 (1998)
14EEKuen-Jong Lee, Wei-Lun Wang, Jhing-Fa Wang: A General Structure of Feedback Shift Registers for Built-In Self Test. J. Inf. Sci. Eng. 14(3): 645-667 (1998)
13EEKuen-Jong Lee, Cheng-Hsuing Kuo: Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters. J. Inf. Sci. Eng. 14(4): 863-890 (1998)
1997
12EETsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee: Built-in current sensor designs based on the bulk-driven technique. Asian Test Symposium 1997: 384-
1996
11EEKuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai: Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. Asian Test Symposium 1996: 100-
10EEKuen-Jong Lee, Jing-Jou Tang: Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. Asian Test Symposium 1996: 165-171
1995
9 Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee: An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). ISCAS 1995: 393-396
8 Kuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee: A New Architecture for Analog Boundary Scan. ISCAS 1995: 409-412
7EEJing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu: A practical current sensing technique for IDDQ testing. IEEE Trans. VLSI Syst. 3(2): 302-310 (1995)
6EEKuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer: An integrated system for assigning signal flow directions to CMOS transistors. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1445-1458 (1995)
1994
5EEKuen-Jong Lee, Charles Njinda, Melvin A. Breuer: SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 625-637 (1994)
1992
4EEKuen-Jong Lee, Charles Njinda, Melvin A. Breuer: SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. DAC 1992: 26-29
3 Wei-Lun Wang, Jhing-Fa Wang, Kuen-Jong Lee: A Fast Testing Method for Sequential Circuits at the State Trasition Level. ITC 1992: 514-519
2EEKuen-Jong Lee, Melvin A. Breuer: Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 659-670 (1992)
1990
1 Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer: A New Method for Assigning Signal Flow Directions to MOS Transistors. ICCAD 1990: 492-495

Coauthor Index

1Melvin A. Breuer [1] [2] [4] [5] [6] [39] [40] [41]
2Soon-Jyh Chang [35] [36]
3Chung-Ho Chen [42] [43]
4Jih-Jeen Chen [16] [18] [22] [33] [34]
5Chia-Yi Chu [38]
6Wern-Yih Duh [17]
7Rajiv Gupta [1] [6]
8Chia-Ming Ho [37]
9Yu-Ting Hong [38]
10Tong-Yu Hsieh [39] [40] [41]
11Shaing-Jer Hsu [37]
12Cheng-Hua Huang [16] [18]
13Cheng-I. Huang [24]
14Chih-Haur Huang [36]
15Min-Cheng Huang [12]
16Tsung-Chu Huang [11] [12] [19] [20] [22] [25] [28] [29] [30]
17Sheng-Yih Jeng [8]
18Cheng-Hsuing Kuo [13]
19Tian-Pao Lee [8]
20Bin-Da Liu [7] [9] [15]
21Tai-Hua Lu [42] [43]
22Charles Njinda [4] [5]
23Chau-chin Su [32]
24Jing-Jou Tang [7] [9] [10] [11] [15] [17] [19]
25Cheng-Liang Tsai [11]
26Ruei-Shiuan Tzeng [35]
27Chih-Nan Wang [6]
28Jhing-Fa Wang [3] [14] [27]
29Wei-Lun Wang [3] [14] [23] [27] [31]
30Yun-Che Wen [21] [26]
31Chia-Kai Yang [34]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)