| 2008 |
|---|
| 43 | EE | Tai-Hua Lu,
Chung-Ho Chen,
Kuen-Jong Lee:
A hybrid self-testing methodology of processor cores.
ISCAS 2008: 3378-3381 |
| 42 | EE | Tai-Hua Lu,
Chung-Ho Chen,
Kuen-Jong Lee:
A hybrid software-based self-testing methodology for embedded processor.
SAC 2008: 1528-1534 |
| 41 | EE | Tong-Yu Hsieh,
Kuen-Jong Lee,
Melvin A. Breuer:
An Error Rate Based Test Methodology to Support Error-Tolerance.
IEEE Transactions on Reliability 57(1): 204-214 (2008) |
| 2007 |
|---|
| 40 | EE | Tong-Yu Hsieh,
Kuen-Jong Lee,
Melvin A. Breuer:
Reduction of detected acceptable faults for yield improvement via error-tolerance.
DATE 2007: 1599-1604 |
| 2006 |
|---|
| 39 | EE | Tong-Yu Hsieh,
Kuen-Jong Lee,
Melvin A. Breuer:
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance.
VTS 2006: 130-135 |
| 2005 |
|---|
| 38 | EE | Kuen-Jong Lee,
Chia-Yi Chu,
Yu-Ting Hong:
An embedded processor based SOC test platform.
ISCAS (3) 2005: 2983-2986 |
| 2004 |
|---|
| 37 | EE | Kuen-Jong Lee,
Shaing-Jer Hsu,
Chia-Ming Ho:
Test Power Reduction with Multiple Capture Orders.
Asian Test Symposium 2004: 26-31 |
| 36 | EE | Chih-Haur Huang,
Kuen-Jong Lee,
Soon-Jyh Chang:
A Low-Cost Diagnosis Methodology for Pipelined A/D Converters.
Asian Test Symposium 2004: 296-301 |
| 2003 |
|---|
| 35 | EE | Kuen-Jong Lee,
Soon-Jyh Chang,
Ruei-Shiuan Tzeng:
A Sigma-Delta Modulation Based BIST Scheme for A/D Converters.
Asian Test Symposium 2003: 124-129 |
| 34 | EE | Jih-Jeen Chen,
Chia-Kai Yang,
Kuen-Jong Lee:
Test pattern generation and clock disabling for simultaneous test time and power reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 363-370 (2003) |
| 2002 |
|---|
| 33 | EE | Kuen-Jong Lee,
Jih-Jeen Chen:
Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling.
Asian Test Symposium 2002: 338- |
| 32 | EE | Kuen-Jong Lee,
Chau-chin Su:
Guest Editorial.
J. Electronic Testing 18(1): 15-16 (2002) |
| 31 | EE | Wei-Lun Wang,
Kuen-Jong Lee:
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment.
J. Electronic Testing 18(1): 43-53 (2002) |
| 30 | EE | Kuen-Jong Lee,
Tsung-Chu Huang:
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.
J. Electronic Testing 18(6): 627-636 (2002) |
| 2001 |
|---|
| 29 | EE | Tsung-Chu Huang,
Kuen-Jong Lee:
A Low-Power LFSR Architecture.
Asian Test Symposium 2001: 470 |
| 28 | | Tsung-Chu Huang,
Kuen-Jong Lee:
A token scan architecture for low power testing.
ITC 2001: 660-669 |
| 27 | EE | Wei-Lun Wang,
Kuen-Jong Lee,
Jhing-Fa Wang:
An on-chip march pattern generator for testing embedded memory cores.
IEEE Trans. VLSI Syst. 9(5): 730-735 (2001) |
| 26 | EE | Yun-Che Wen,
Kuen-Jong Lee:
Analysis and generation of control and observation structures foranalog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 165-171 (2001) |
| 25 | EE | Tsung-Chu Huang,
Kuen-Jong Lee:
Reduction of power consumption in scan-based circuits during testapplication by an input control technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 911-917 (2001) |
| 2000 |
|---|
| 24 | EE | Kuen-Jong Lee,
Cheng-I. Huang:
A hierarchical test control architecture for core based design.
Asian Test Symposium 2000: 248-253 |
| 23 | EE | Wei-Lun Wang,
Kuen-Jong Lee:
Accelerated test pattern generators for mixed-mode BIST environments.
Asian Test Symposium 2000: 368-373 |
| 22 | EE | Kuen-Jong Lee,
Tsung-Chu Huang,
Jih-Jeen Chen:
Peak-power reduction for multiple-scan circuits during test application.
Asian Test Symposium 2000: 453-458 |
| 21 | EE | Yun-Che Wen,
Kuen-Jong Lee:
An on Chip ADC Test Structure.
DATE 2000: 221-225 |
| 1999 |
|---|
| 20 | EE | Tsung-Chu Huang,
Kuen-Jong Lee:
An Input Control Technique for Power Reduction in Scan Circuits During Test Application.
Asian Test Symposium 1999: 315-320 |
| 19 | EE | Kuen-Jong Lee,
Jing-Jou Tang,
Tsung-Chu Huang:
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults.
ACM Trans. Design Autom. Electr. Syst. 4(2): 194-218 (1999) |
| 18 | EE | Kuen-Jong Lee,
Jih-Jeen Chen,
Cheng-Hua Huang:
Broadcasting test patterns to multiple circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1793-1802 (1999) |
| 1998 |
|---|
| 17 | EE | Kuen-Jong Lee,
Jing-Jou Tang,
Wern-Yih Duh:
On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation.
Asian Test Symposium 1998: 113-118 |
| 16 | EE | Kuen-Jong Lee,
Jih-Jeen Chen,
Cheng-Hua Huang:
Using a single input to support multiple scan chains.
ICCAD 1998: 74-78 |
| 15 | EE | Jing-Jou Tang,
Kuen-Jong Lee,
Bin-Da Liu:
A graph representation for programmable logic arrays to facilitate testing and logic design.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1030-1043 (1998) |
| 14 | EE | Kuen-Jong Lee,
Wei-Lun Wang,
Jhing-Fa Wang:
A General Structure of Feedback Shift Registers for Built-In Self Test.
J. Inf. Sci. Eng. 14(3): 645-667 (1998) |
| 13 | EE | Kuen-Jong Lee,
Cheng-Hsuing Kuo:
Concurrent Error Detection, Diagnosis, and Fault Tolerance for Switched-Capacitor Filters.
J. Inf. Sci. Eng. 14(4): 863-890 (1998) |
| 1997 |
|---|
| 12 | EE | Tsung-Chu Huang,
Min-Cheng Huang,
Kuen-Jong Lee:
Built-in current sensor designs based on the bulk-driven technique.
Asian Test Symposium 1997: 384- |
| 1996 |
|---|
| 11 | EE | Kuen-Jong Lee,
Jing-Jou Tang,
Tsung-Chu Huang,
Cheng-Liang Tsai:
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.
Asian Test Symposium 1996: 100- |
| 10 | EE | Kuen-Jong Lee,
Jing-Jou Tang:
Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.
Asian Test Symposium 1996: 165-171 |
| 1995 |
|---|
| 9 | | Jing-Jou Tang,
Bin-Da Liu,
Kuen-Jong Lee:
An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs).
ISCAS 1995: 393-396 |
| 8 | | Kuen-Jong Lee,
Sheng-Yih Jeng,
Tian-Pao Lee:
A New Architecture for Analog Boundary Scan.
ISCAS 1995: 409-412 |
| 7 | EE | Jing-Jou Tang,
Kuen-Jong Lee,
Bin-Da Liu:
A practical current sensing technique for IDDQ testing.
IEEE Trans. VLSI Syst. 3(2): 302-310 (1995) |
| 6 | EE | Kuen-Jong Lee,
Chih-Nan Wang,
Rajiv Gupta,
Melvin A. Breuer:
An integrated system for assigning signal flow directions to CMOS transistors.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1445-1458 (1995) |
| 1994 |
|---|
| 5 | EE | Kuen-Jong Lee,
Charles Njinda,
Melvin A. Breuer:
SWiTEST: a switch level test generation system for CMOS combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 625-637 (1994) |
| 1992 |
|---|
| 4 | EE | Kuen-Jong Lee,
Charles Njinda,
Melvin A. Breuer:
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits.
DAC 1992: 26-29 |
| 3 | | Wei-Lun Wang,
Jhing-Fa Wang,
Kuen-Jong Lee:
A Fast Testing Method for Sequential Circuits at the State Trasition Level.
ITC 1992: 514-519 |
| 2 | EE | Kuen-Jong Lee,
Melvin A. Breuer:
Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 659-670 (1992) |
| 1990 |
|---|
| 1 | | Kuen-Jong Lee,
Rajiv Gupta,
Melvin A. Breuer:
A New Method for Assigning Signal Flow Directions to MOS Transistors.
ICCAD 1990: 492-495 |
