| 2008 |
|---|
| 10 | EE | Adriel Cheng,
Cheng-Chew Lim,
Yihe Sun,
Hu He,
Zhixiong Zhou,
Ting Lei:
Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC.
DELTA 2008: 20-25 |
| 2007 |
|---|
| 9 | EE | Zhixiong Zhou,
Hu He,
Yanjun Zhang,
Yihe Sun,
Adriel Cheng:
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture.
ASAP 2007: 371-376 |
| 8 | EE | Yang Xu,
Hu He,
Zhou Zhixiong,
Yanjun Zhang,
Yihe Sun:
Heuristic on a Novel Power Management System Cooperating with Compiler.
J. Low Power Electronics 3(1): 22-27 (2007) |
| 2006 |
|---|
| 7 | | Zhou Zhixiong,
Yang Xu,
He Hu,
Yihe Sun:
A Retargetable Compiler of VLIW ASIP for Media Signal Processing.
ESA 2006: 46-52 |
| 6 | EE | Zheng Shen,
Hu He,
Yanjun Zhang,
Yihe Sun:
VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design.
IIH-MSP 2006: 587-592 |
| 2005 |
|---|
| 5 | EE | Yanjun Zhang,
Hu He,
Yihe Sun:
A new register file access architecture for software pipelining in VLIW processors.
ASP-DAC 2005: 627-630 |
| 2003 |
|---|
| 4 | EE | He Hu,
Yihe Sun:
Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST.
Asian Test Symposium 2003: 507 |
| 3 | EE | Xingjun Wu,
Hongyi Chen,
Yihe Sun,
Weixin Gai:
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems.
VLSI Signal Processing 33(1-2): 191-197 (2003) |
| 2002 |
|---|
| 2 | | Ke Jiang,
Yihe Sun:
An Optimizing Search Method of Systolic Array Design.
IASTED PDCS 2002: 573-577 |
| 2001 |
|---|
| 1 | | Lei Xu,
Yihe Sun,
Hongyi Chen:
Scan array solution for testing power and testing time.
ITC 2001: 652-659 |
