| 2008 |
|---|
| 15 | EE | Yu Pang,
Katarzyna Radecka:
Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform.
DAC 2008: 397-402 |
| 2007 |
|---|
| 14 | EE | Zeljko Zilic,
Katarzyna Radecka,
Ali Kazamiphur:
Reversible circuit technology mapping from non-reversible specifications.
DATE 2007: 558-563 |
| 13 | EE | Zeljko Zilic,
Katarzyna Radecka:
Scaling and Better Approximating Quantum Fourier Transform by Higher Radices.
IEEE Trans. Computers 56(2): 202-207 (2007) |
| 2006 |
|---|
| 12 | EE | Rong Zhang,
Zeljko Zilic,
Katarzyna Radecka:
Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes.
VTS 2006: 186-191 |
| 2004 |
|---|
| 11 | EE | Ahmed Usman Khalid,
Zeljko Zilic,
Katarzyna Radecka:
FPGA Emulation of Quantum Circuits.
ICCD 2004: 310-315 |
| 10 | EE | Man Wah Chiang,
Zeljko Zilic,
Jean-Samuel Chenard,
Katarzyna Radecka:
Architectures of Increased Availability Wireless Sensor Network Nodes.
ITC 2004: 1232-1241 |
| 9 | EE | Katarzyna Radecka,
Zeljko Zilic:
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set.
IEEE Trans. Computers 53(5): 628-640 (2004) |
| 2002 |
|---|
| 8 | EE | Katarzyna Radecka,
Zeljko Zilic:
Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms.
ICCAD 2002: 128-131 |
| 7 | EE | Zeljko Zilic,
Katarzyna Radecka:
The Role of Super-Fast Transforms in Speeding Up Quantum Computations.
ISMVL 2002: 129-135 |
| 6 | EE | Katarzyna Radecka,
Zeljko Zilic:
Identifying Redundant Wire Replacements for Synthesis and Verification.
VLSI Design 2002: 517-523 |
| 2001 |
|---|
| 5 | | Katarzyna Radecka,
Zeljko Zilic:
Arithmetic Transforms for Verifying Compositions of Sequential Datapaths.
ICCD 2001: 348-353 |
| 4 | | Zeljko Zilic,
Katarzyna Radecka:
: Identifying redundant gate replacements in verification by error modeling.
ITC 2001: 803-812 |
| 2000 |
|---|
| 3 | EE | Katarzyna Radecka,
Zeljko Zilic:
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling.
VTS 2000: 271-280 |
| 1999 |
|---|
| 2 | EE | Zeljko Zilic,
Katarzyna Radecka:
On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields.
ISSAC 1999: 67-74 |
| 1997 |
|---|
| 1 | EE | Katarzyna Radecka,
Janusz Rajski,
Jerzy Tyszer:
Arithmetic built-in self-test for DSP cores.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1358-1369 (1997) |
